drivers/pinctrl/nxp/pinctrl-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <mapmem.h>
   9 #include <dm/device_compat.h>
  10 #include <dm/devres.h>
  11 #include <linux/io.h>
  12 #include <linux/err.h>
  13 #include <dm.h>
  14 #include <dm/pinctrl.h>
  15
  16 #include "pinctrl-imx.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  21 {
  22         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
  23         struct imx_pinctrl_soc_info *info = priv->info;
  24         int node = dev_of_offset(config);
  25         const struct fdt_property *prop;
  26         u32 *pin_data;
  27         int npins, size, pin_size;
  28         int mux_reg, conf_reg, input_reg;
  29         u32 input_val, mux_mode, config_val;
  30         u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
  31         int i, j = 0;
  32
  33         dev_dbg(dev, "%s: %s\n", __func__, config->name);
  34
  35         if (info->flags & IMX8_USE_SCU)
  36                 pin_size = SHARE_IMX8_PIN_SIZE;
  37         else if (info->flags & SHARE_MUX_CONF_REG)
  38                 pin_size = SHARE_FSL_PIN_SIZE;
  39         else
  40                 pin_size = FSL_PIN_SIZE;
  41
  42         prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
  43         if (!prop) {
  44                 dev_err(dev, "No fsl,pins property in node %s\n", config->name);
  45                 return -EINVAL;
  46         }
  47
  48         if (!size || size % pin_size) {
  49                 dev_err(dev, "Invalid fsl,pins property in node %s\n",
  50                         config->name);
  51                 return -EINVAL;
  52         }
  53
  54         pin_data = devm_kzalloc(dev, size, 0);
  55         if (!pin_data)
  56                 return -ENOMEM;
  57
  58         if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
  59                                  pin_data, size >> 2)) {
  60                 dev_err(dev, "Error reading pin data.\n");
  61                 devm_kfree(dev, pin_data);
  62                 return -EINVAL;
  63         }
  64
  65         npins = size / pin_size;
  66
  67         if (info->flags & IMX8_USE_SCU) {
  68                 imx_pinctrl_scu_conf_pins(info, pin_data, npins);
  69         } else {
  70                 /*
  71                  * Refer to linux documentation for details:
  72                  * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
  73                  */
  74                 for (i = 0; i < npins; i++) {
  75                         mux_reg = pin_data[j++];
  76
  77                         if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
  78                                 mux_reg = -1;
  79
  80                         if (info->flags & SHARE_MUX_CONF_REG) {
  81                                 conf_reg = mux_reg;
  82                         } else {
  83                                 conf_reg = pin_data[j++];
  84                                 if (!(info->flags & ZERO_OFFSET_VALID) &&
  85                                     !conf_reg)
  86                                         conf_reg = -1;
  87                         }
  88
  89                         if ((mux_reg == -1) || (conf_reg == -1)) {
  90                                 dev_err(dev, "Error mux_reg or conf_reg\n");
  91                                 devm_kfree(dev, pin_data);
  92                                 return -EINVAL;
  93                         }
  94
  95                         input_reg = pin_data[j++];
  96                         mux_mode = pin_data[j++];
  97                         input_val = pin_data[j++];
  98                         config_val = pin_data[j++];
  99
 100                         dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
 101                                 "input_reg 0x%x, mux_mode 0x%x, "
 102                                 "input_val 0x%x, config_val 0x%x\n",
 103                                 mux_reg, conf_reg, input_reg, mux_mode,
 104                                 input_val, config_val);
 105
 106                         if (config_val & IMX_PAD_SION)
 107                                 mux_mode |= IOMUXC_CONFIG_SION;
 108
 109                         config_val &= ~IMX_PAD_SION;
 110
 111                         /* Set Mux */
 112                         if (info->flags & SHARE_MUX_CONF_REG) {
 113                                 clrsetbits_le32(info->base + mux_reg,
 114                                                 info->mux_mask,
 115                                                 mux_mode << mux_shift);
 116                         } else {
 117                                 writel(mux_mode, info->base + mux_reg);
 118                         }
 119
 120                         dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
 121                                 mux_reg, mux_mode);
 122
 123                         /*
 124                          * Set select input
 125                          *
 126                          * If the select input value begins with 0xff,
 127                          * it's a quirky select input and the value should
 128                          * be interpreted as below.
 129                          *     31     23      15      7        0
 130                          *     | 0xff | shift | width | select |
 131                          * It's used to work around the problem that the
 132                          * select input for some pin is not implemented in
 133                          * the select input register but in some general
 134                          * purpose register. We encode the select input
 135                          * value, width and shift of the bit field into
 136                          * input_val cell of pin function ID in device tree,
 137                          * and then decode them here for setting up the select
 138                          * input bits in general purpose register.
 139                          */
 140
 141                         if (input_val >> 24 == 0xff) {
 142                                 u32 val = input_val;
 143                                 u8 select = val & 0xff;
 144                                 u8 width = (val >> 8) & 0xff;
 145                                 u8 shift = (val >> 16) & 0xff;
 146                                 u32 mask = ((1 << width) - 1) << shift;
 147                                 /*
 148                                  * The input_reg[i] here is actually some
 149                                  * IOMUXC general purpose register, not
 150                                  * regular select input register.
 151                                  */
 152                                 val = readl(info->base + input_reg);
 153                                 val &= ~mask;
 154                                 val |= select << shift;
 155                                 writel(val, info->base + input_reg);
 156                         } else if (input_reg) {
 157                                 /*
 158                                  * Regular select input register can never be
 159                                  * at offset 0, and we only print register
 160                                  * value for regular case.
 161                                  */
 162                                 if (info->input_sel_base)
 163                                         writel(input_val,
 164                                                info->input_sel_base +
 165                                                input_reg);
 166                                 else
 167                                         writel(input_val,
 168                                                info->base + input_reg);
 169
 170                                 dev_dbg(dev, "select_input: offset 0x%x val "
 171                                         "0x%x\n", input_reg, input_val);
 172                         }
 173
 174                         /* Set config */
 175                         if (!(config_val & IMX_NO_PAD_CTL)) {
 176                                 if (info->flags & SHARE_MUX_CONF_REG) {
 177                                         clrsetbits_le32(info->base + conf_reg,
 178                                                         ~info->mux_mask,
 179                                                         config_val);
 180                                 } else {
 181                                         writel(config_val,
 182                                                info->base + conf_reg);
 183                                 }
 184
 185                                 dev_dbg(dev, "write config: offset 0x%x val "
 186                                         "0x%x\n", conf_reg, config_val);
 187                         }
 188                 }
 189         }
 190
 191         devm_kfree(dev, pin_data);
 192
 193         return 0;
 194 }
 195
 196 const struct pinctrl_ops imx_pinctrl_ops  = {
 197         .set_state = imx_pinctrl_set_state,
 198 };
 199
 200 int imx_pinctrl_probe(struct udevice *dev,
 201                       struct imx_pinctrl_soc_info *info)
 202 {
 203         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 204         int node = dev_of_offset(dev), ret;
 205         struct fdtdec_phandle_args arg;
 206         fdt_addr_t addr;
 207         fdt_size_t size;
 208
 209         if (!info) {
 210                 dev_err(dev, "wrong pinctrl info\n");
 211                 return -EINVAL;
 212         }
 213
 214         priv->dev = dev;
 215         priv->info = info;
 216
 217         if (info->flags & IMX8_USE_SCU)
 218                 return 0;
 219
 220         addr = devfdt_get_addr_size_index(dev, 0, &size);
 221         if (addr == FDT_ADDR_T_NONE)
 222                 return -EINVAL;
 223
 224         info->base = map_sysmem(addr, size);
 225         if (!info->base)
 226                 return -ENOMEM;
 227         priv->info = info;
 228
 229         info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
 230         /*
 231          * Refer to linux documentation for details:
 232          * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
 233          */
 234         if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
 235                 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
 236                                                      node, "fsl,input-sel",
 237                                                      NULL, 0, 0, &arg);
 238                 if (ret) {
 239                         dev_err(dev, "iomuxc fsl,input-sel property not found\n");
 240                         return -EINVAL;
 241                 }
 242
 243                 addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
 244                                             &size);
 245                 if (addr == FDT_ADDR_T_NONE)
 246                         return -EINVAL;
 247
 248                 info->input_sel_base = map_sysmem(addr, size);
 249                 if (!info->input_sel_base)
 250                         return -ENOMEM;
 251         }
 252
 253         dev_dbg(dev, "initialized IMX pinctrl driver\n");
 254
 255         return 0;
 256 }
 257
 258 int imx_pinctrl_remove(struct udevice *dev)
 259 {
 260         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 261         struct imx_pinctrl_soc_info *info = priv->info;
 262
 263         if (info->flags & IMX8_USE_SCU)
 264                 return 0;
 265
 266         if (info->input_sel_base)
 267                 unmap_sysmem(info->input_sel_base);
 268         if (info->base)
 269                 unmap_sysmem(info->base);
 270
 271         return 0;
 272 }