2 * U-Boot Marvell 37xx SoC pinctrl driver
4 * Copyright (C) 2017 Stefan Roese <sr@denx.de>
6 * This driver is based on the Linux driver version, which is:
7 * Copyright (C) 2017 Marvell
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Additionally parts are derived from the Meson U-Boot pinctrl driver,
12 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
13 * Based on code from Linux kernel:
14 * Copyright (C) 2016 Endless Mobile, Inc.
16 * SPDX-License-Identifier: GPL-2.0+
17 * https://spdx.org/licenses
23 #include <dm/device-internal.h>
25 #include <dm/pinctrl.h>
31 #include <asm/system.h>
34 DECLARE_GLOBAL_DATA_PTR;
37 #define INPUT_VAL 0x10
38 #define OUTPUT_VAL 0x18
39 #define OUTPUT_CTL 0x20
40 #define SELECTION 0x30
44 #define IRQ_STATUS 0x10
48 #define GPIO_PER_REG 32
51 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
52 * The pins of a pinmux groups are composed of one or two groups of contiguous
54 * @name: Name of the pin group, used to lookup the group.
55 * @start_pins: Index of the first pin of the main range of pins belonging to
57 * @npins: Number of pins included in the first range
58 * @reg_mask: Bit mask matching the group in the selection register
59 * @extra_pins: Index of the first pin of the optional second range of pins
60 * belonging to the group
61 * @npins: Number of pins included in the second optional range
62 * @funcs: A list of pinmux functions that can be selected for this group.
63 * @pins: List of the pins included in the group
65 struct armada_37xx_pin_group {
67 unsigned int start_pin;
71 unsigned int extra_pin;
72 unsigned int extra_npins;
73 const char *funcs[NB_FUNCS];
77 struct armada_37xx_pin_data {
80 struct armada_37xx_pin_group *groups;
84 struct armada_37xx_pmx_func {
90 struct armada_37xx_pinctrl {
92 const struct armada_37xx_pin_data *data;
94 struct pinctrl_dev *pctl_dev;
95 struct armada_37xx_pin_group *groups;
97 struct armada_37xx_pmx_func *funcs;
101 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
104 .start_pin = _start, \
108 .funcs = {_func1, _func2} \
111 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
114 .start_pin = _start, \
118 .funcs = {_func1, "gpio"} \
121 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
124 .start_pin = _start, \
127 .val = {_val1, _val2}, \
128 .funcs = {_func1, "gpio"} \
131 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
134 .start_pin = _start, \
137 .val = {_v1, _v2, _v3}, \
138 .funcs = {_f1, _f2, "gpio"} \
141 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
145 .start_pin = _start, \
149 .extra_pin = _start2, \
150 .extra_npins = _nr2, \
151 .funcs = {_f1, _f2} \
154 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
155 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
156 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
157 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
158 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
159 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
160 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
161 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
162 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
163 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
164 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
165 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
166 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
167 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
168 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
169 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
170 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
171 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
172 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
173 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
174 18, 2, "gpio", "uart"),
175 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
176 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
177 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
178 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
182 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
183 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
184 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
185 PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"),
186 PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
187 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
188 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
189 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
190 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
191 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
195 const struct armada_37xx_pin_data armada_37xx_pin_nb = {
198 .groups = armada_37xx_nb_groups,
199 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
202 const struct armada_37xx_pin_data armada_37xx_pin_sb = {
205 .groups = armada_37xx_sb_groups,
206 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
209 static inline void armada_37xx_update_reg(unsigned int *reg,
212 /* We never have more than 2 registers */
213 if (offset >= GPIO_PER_REG) {
214 offset -= GPIO_PER_REG;
219 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
224 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
225 if (!strcmp(grp->funcs[f], func))
231 static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
233 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
235 return info->ngroups;
238 static const char *armada_37xx_pmx_dummy_name = "_dummy";
240 static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
243 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
245 if (!info->groups[selector].name)
246 return armada_37xx_pmx_dummy_name;
248 return info->groups[selector].name;
251 static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
253 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
258 static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
261 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
263 return info->funcs[selector].name;
266 static int armada_37xx_pmx_set_by_name(struct udevice *dev,
268 struct armada_37xx_pin_group *grp)
270 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
271 unsigned int reg = SELECTION;
272 unsigned int mask = grp->reg_mask;
275 dev_dbg(info->dev, "enable function %s group %s\n",
278 func = armada_37xx_get_func_reg(grp, name);
283 val = grp->val[func];
285 clrsetbits_le32(info->base + reg, mask, val);
290 static int armada_37xx_pmx_group_set(struct udevice *dev,
291 unsigned group_selector,
292 unsigned func_selector)
294 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
295 struct armada_37xx_pin_group *grp = &info->groups[group_selector];
296 const char *name = info->funcs[func_selector].name;
298 return armada_37xx_pmx_set_by_name(dev, name, grp);
302 * armada_37xx_add_function() - Add a new function to the list
303 * @funcs: array of function to add the new one
304 * @funcsize: size of the remaining space for the function
305 * @name: name of the function to add
307 * If it is a new function then create it by adding its name else
308 * increment the number of group associated to this function.
310 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
311 int *funcsize, const char *name)
318 while (funcs->ngroups) {
319 /* function already there */
320 if (strcmp(funcs->name, name) == 0) {
329 /* append new unique function */
338 * armada_37xx_fill_group() - complete the group array
339 * @info: info driver instance
341 * Based on the data available from the armada_37xx_pin_group array
342 * completes the last member of the struct for each function: the list
343 * of the groups associated to this function.
346 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
348 int n, num = 0, funcsize = info->data->nr_pins;
350 for (n = 0; n < info->ngroups; n++) {
351 struct armada_37xx_pin_group *grp = &info->groups[n];
354 grp->pins = devm_kzalloc(info->dev,
355 (grp->npins + grp->extra_npins) *
356 sizeof(*grp->pins), GFP_KERNEL);
360 for (i = 0; i < grp->npins; i++)
361 grp->pins[i] = grp->start_pin + i;
363 for (j = 0; j < grp->extra_npins; j++)
364 grp->pins[i+j] = grp->extra_pin + j;
366 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
368 /* check for unique functions and count groups */
369 ret = armada_37xx_add_function(info->funcs, &funcsize,
371 if (ret == -EOVERFLOW)
373 "More functions than pins(%d)\n",
374 info->data->nr_pins);
387 * armada_37xx_fill_funcs() - complete the funcs array
388 * @info: info driver instance
390 * Based on the data available from the armada_37xx_pin_group array
391 * completes the last two member of the struct for each group:
392 * - the list of the pins included in the group
393 * - the list of pinmux functions that can be selected for this group
396 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
398 struct armada_37xx_pmx_func *funcs = info->funcs;
401 for (n = 0; n < info->nfuncs; n++) {
402 const char *name = funcs[n].name;
406 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
407 sizeof(*(funcs[n].groups)),
409 if (!funcs[n].groups)
412 groups = funcs[n].groups;
414 for (g = 0; g < info->ngroups; g++) {
415 struct armada_37xx_pin_group *gp = &info->groups[g];
418 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
419 if (strcmp(gp->funcs[f], name) == 0) {
429 static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
431 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
432 unsigned int reg = INPUT_VAL;
433 unsigned int val, mask;
435 armada_37xx_update_reg(®, offset);
438 val = readl(info->base + reg);
440 return (val & mask) != 0;
443 static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
446 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
447 unsigned int reg = OUTPUT_VAL;
448 unsigned int mask, val;
450 armada_37xx_update_reg(®, offset);
452 val = value ? mask : 0;
454 clrsetbits_le32(info->base + reg, mask, val);
459 static int armada_37xx_gpio_get_direction(struct udevice *dev,
462 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
463 unsigned int reg = OUTPUT_EN;
464 unsigned int val, mask;
466 armada_37xx_update_reg(®, offset);
468 val = readl(info->base + reg);
476 static int armada_37xx_gpio_direction_input(struct udevice *dev,
479 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
480 unsigned int reg = OUTPUT_EN;
483 armada_37xx_update_reg(®, offset);
486 clrbits_le32(info->base + reg, mask);
491 static int armada_37xx_gpio_direction_output(struct udevice *dev,
492 unsigned int offset, int value)
494 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
495 unsigned int reg = OUTPUT_EN;
498 armada_37xx_update_reg(®, offset);
501 setbits_le32(info->base + reg, mask);
503 /* And set the requested value */
504 return armada_37xx_gpio_set(dev, offset, value);
507 static int armada_37xx_gpio_probe(struct udevice *dev)
509 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
510 struct gpio_dev_priv *uc_priv;
512 uc_priv = dev_get_uclass_priv(dev);
513 uc_priv->bank_name = info->data->name;
514 uc_priv->gpio_count = info->data->nr_pins;
519 static const struct dm_gpio_ops armada_37xx_gpio_ops = {
520 .set_value = armada_37xx_gpio_set,
521 .get_value = armada_37xx_gpio_get,
522 .get_function = armada_37xx_gpio_get_direction,
523 .direction_input = armada_37xx_gpio_direction_input,
524 .direction_output = armada_37xx_gpio_direction_output,
527 static struct driver armada_37xx_gpio_driver = {
528 .name = "armada-37xx-gpio",
530 .probe = armada_37xx_gpio_probe,
531 .ops = &armada_37xx_gpio_ops,
534 static int armada_37xx_gpiochip_register(struct udevice *parent,
535 struct armada_37xx_pinctrl *info)
537 const void *blob = gd->fdt_blob;
538 int node = dev_of_offset(parent);
539 struct uclass_driver *drv;
545 /* Lookup GPIO driver */
546 drv = lists_uclass_lookup(UCLASS_GPIO);
548 puts("Cannot find GPIO driver\n");
552 fdt_for_each_subnode(subnode, blob, node) {
553 if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
561 name = calloc(1, 32);
562 sprintf(name, "armada-37xx-gpio");
564 /* Create child device UCLASS_GPIO and bind it */
565 device_bind(parent, &armada_37xx_gpio_driver, name, NULL, subnode,
567 dev_set_of_offset(dev, subnode);
572 const struct pinctrl_ops armada_37xx_pinctrl_ops = {
573 .get_groups_count = armada_37xx_pmx_get_groups_count,
574 .get_group_name = armada_37xx_pmx_get_group_name,
575 .get_functions_count = armada_37xx_pmx_get_funcs_count,
576 .get_function_name = armada_37xx_pmx_get_func_name,
577 .pinmux_group_set = armada_37xx_pmx_group_set,
578 .set_state = pinctrl_generic_set_state,
581 int armada_37xx_pinctrl_probe(struct udevice *dev)
583 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
584 const struct armada_37xx_pin_data *pin_data;
587 info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
588 pin_data = info->data;
590 info->base = (void __iomem *)devfdt_get_addr(dev);
592 pr_err("unable to find regmap\n");
596 info->groups = pin_data->groups;
597 info->ngroups = pin_data->ngroups;
600 * we allocate functions for number of pins and hope there are
601 * fewer unique functions than pins available
603 info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
604 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
609 ret = armada_37xx_fill_group(info);
613 ret = armada_37xx_fill_func(info);
617 ret = armada_37xx_gpiochip_register(dev, info);
624 static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
626 .compatible = "marvell,armada3710-sb-pinctrl",
627 .data = (ulong)&armada_37xx_pin_sb,
630 .compatible = "marvell,armada3710-nb-pinctrl",
631 .data = (ulong)&armada_37xx_pin_nb,
636 U_BOOT_DRIVER(armada_37xx_pinctrl) = {
637 .name = "armada-37xx-pinctrl",
638 .id = UCLASS_PINCTRL,
639 .of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
640 .probe = armada_37xx_pinctrl_probe,
641 .priv_auto_alloc_size = sizeof(struct armada_37xx_pinctrl),
642 .ops = &armada_37xx_pinctrl_ops,