2 * U-Boot Marvell 37xx SoC pinctrl driver
4 * Copyright (C) 2017 Stefan Roese <sr@denx.de>
6 * This driver is based on the Linux driver version, which is:
7 * Copyright (C) 2017 Marvell
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Additionally parts are derived from the Meson U-Boot pinctrl driver,
12 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
13 * Based on code from Linux kernel:
14 * Copyright (C) 2016 Endless Mobile, Inc.
16 * SPDX-License-Identifier: GPL-2.0+
17 * https://spdx.org/licenses
23 #include <dm/device-internal.h>
25 #include <dm/pinctrl.h>
31 #include <asm/system.h>
34 DECLARE_GLOBAL_DATA_PTR;
37 #define INPUT_VAL 0x10
38 #define OUTPUT_VAL 0x18
39 #define OUTPUT_CTL 0x20
40 #define SELECTION 0x30
44 #define IRQ_STATUS 0x10
48 #define GPIO_PER_REG 32
51 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
52 * The pins of a pinmux groups are composed of one or two groups of contiguous
54 * @name: Name of the pin group, used to lookup the group.
55 * @start_pins: Index of the first pin of the main range of pins belonging to
57 * @npins: Number of pins included in the first range
58 * @reg_mask: Bit mask matching the group in the selection register
59 * @extra_pins: Index of the first pin of the optional second range of pins
60 * belonging to the group
61 * @npins: Number of pins included in the second optional range
62 * @funcs: A list of pinmux functions that can be selected for this group.
63 * @pins: List of the pins included in the group
65 struct armada_37xx_pin_group {
67 unsigned int start_pin;
71 unsigned int extra_pin;
72 unsigned int extra_npins;
73 const char *funcs[NB_FUNCS];
77 struct armada_37xx_pin_data {
80 struct armada_37xx_pin_group *groups;
84 struct armada_37xx_pmx_func {
90 struct armada_37xx_pinctrl {
92 const struct armada_37xx_pin_data *data;
94 struct pinctrl_dev *pctl_dev;
95 struct armada_37xx_pin_group *groups;
97 struct armada_37xx_pmx_func *funcs;
101 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
104 .start_pin = _start, \
108 .funcs = {_func1, _func2} \
111 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
114 .start_pin = _start, \
118 .funcs = {_func1, "gpio"} \
121 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
124 .start_pin = _start, \
127 .val = {_val1, _val2}, \
128 .funcs = {_func1, "gpio"} \
131 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
135 .start_pin = _start, \
139 .extra_pin = _start2, \
140 .extra_npins = _nr2, \
141 .funcs = {_f1, _f2} \
144 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
145 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
146 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
147 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
148 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
149 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
150 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
151 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
152 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
153 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
154 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
155 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
156 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
157 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
158 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
159 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
160 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
161 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
162 PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19),
163 BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"),
164 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
165 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
166 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
167 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
171 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
172 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
173 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
174 PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"),
175 PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
176 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
177 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
178 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
179 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
180 PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"),
183 const struct armada_37xx_pin_data armada_37xx_pin_nb = {
186 .groups = armada_37xx_nb_groups,
187 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
190 const struct armada_37xx_pin_data armada_37xx_pin_sb = {
193 .groups = armada_37xx_sb_groups,
194 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
197 static inline void armada_37xx_update_reg(unsigned int *reg,
200 /* We never have more than 2 registers */
201 if (offset >= GPIO_PER_REG) {
202 offset -= GPIO_PER_REG;
207 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
212 for (f = 0; f < NB_FUNCS; f++)
213 if (!strcmp(grp->funcs[f], func))
219 static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
221 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
223 return info->ngroups;
226 static const char *armada_37xx_pmx_dummy_name = "_dummy";
228 static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
231 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
233 if (!info->groups[selector].name)
234 return armada_37xx_pmx_dummy_name;
236 return info->groups[selector].name;
239 static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
241 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
246 static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
249 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
251 return info->funcs[selector].name;
254 static int armada_37xx_pmx_set_by_name(struct udevice *dev,
256 struct armada_37xx_pin_group *grp)
258 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
259 unsigned int reg = SELECTION;
260 unsigned int mask = grp->reg_mask;
263 dev_dbg(info->dev, "enable function %s group %s\n",
266 func = armada_37xx_get_func_reg(grp, name);
271 val = grp->val[func];
273 clrsetbits_le32(info->base + reg, mask, val);
278 static int armada_37xx_pmx_group_set(struct udevice *dev,
279 unsigned group_selector,
280 unsigned func_selector)
282 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
283 struct armada_37xx_pin_group *grp = &info->groups[group_selector];
284 const char *name = info->funcs[func_selector].name;
286 return armada_37xx_pmx_set_by_name(dev, name, grp);
290 * armada_37xx_add_function() - Add a new function to the list
291 * @funcs: array of function to add the new one
292 * @funcsize: size of the remaining space for the function
293 * @name: name of the function to add
295 * If it is a new function then create it by adding its name else
296 * increment the number of group associated to this function.
298 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
299 int *funcsize, const char *name)
306 while (funcs->ngroups) {
307 /* function already there */
308 if (strcmp(funcs->name, name) == 0) {
317 /* append new unique function */
326 * armada_37xx_fill_group() - complete the group array
327 * @info: info driver instance
329 * Based on the data available from the armada_37xx_pin_group array
330 * completes the last member of the struct for each function: the list
331 * of the groups associated to this function.
334 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
336 int n, num = 0, funcsize = info->data->nr_pins;
338 for (n = 0; n < info->ngroups; n++) {
339 struct armada_37xx_pin_group *grp = &info->groups[n];
342 grp->pins = devm_kzalloc(info->dev,
343 (grp->npins + grp->extra_npins) *
344 sizeof(*grp->pins), GFP_KERNEL);
348 for (i = 0; i < grp->npins; i++)
349 grp->pins[i] = grp->start_pin + i;
351 for (j = 0; j < grp->extra_npins; j++)
352 grp->pins[i+j] = grp->extra_pin + j;
354 for (f = 0; f < NB_FUNCS; f++) {
356 /* check for unique functions and count groups */
357 ret = armada_37xx_add_function(info->funcs, &funcsize,
359 if (ret == -EOVERFLOW)
361 "More functions than pins(%d)\n",
362 info->data->nr_pins);
375 * armada_37xx_fill_funcs() - complete the funcs array
376 * @info: info driver instance
378 * Based on the data available from the armada_37xx_pin_group array
379 * completes the last two member of the struct for each group:
380 * - the list of the pins included in the group
381 * - the list of pinmux functions that can be selected for this group
384 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
386 struct armada_37xx_pmx_func *funcs = info->funcs;
389 for (n = 0; n < info->nfuncs; n++) {
390 const char *name = funcs[n].name;
394 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
395 sizeof(*(funcs[n].groups)),
397 if (!funcs[n].groups)
400 groups = funcs[n].groups;
402 for (g = 0; g < info->ngroups; g++) {
403 struct armada_37xx_pin_group *gp = &info->groups[g];
406 for (f = 0; f < NB_FUNCS; f++) {
407 if (strcmp(gp->funcs[f], name) == 0) {
417 static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
419 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
420 unsigned int reg = INPUT_VAL;
421 unsigned int val, mask;
423 armada_37xx_update_reg(®, offset);
426 val = readl(info->base + reg);
428 return (val & mask) != 0;
431 static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
434 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
435 unsigned int reg = OUTPUT_VAL;
436 unsigned int mask, val;
438 armada_37xx_update_reg(®, offset);
440 val = value ? mask : 0;
442 clrsetbits_le32(info->base + reg, mask, val);
447 static int armada_37xx_gpio_get_direction(struct udevice *dev,
450 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
451 unsigned int reg = OUTPUT_EN;
452 unsigned int val, mask;
454 armada_37xx_update_reg(®, offset);
456 val = readl(info->base + reg);
464 static int armada_37xx_gpio_direction_input(struct udevice *dev,
467 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
468 unsigned int reg = OUTPUT_EN;
471 armada_37xx_update_reg(®, offset);
474 clrbits_le32(info->base + reg, mask);
479 static int armada_37xx_gpio_direction_output(struct udevice *dev,
480 unsigned int offset, int value)
482 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
483 unsigned int reg = OUTPUT_EN;
486 armada_37xx_update_reg(®, offset);
489 setbits_le32(info->base + reg, mask);
491 /* And set the requested value */
492 return armada_37xx_gpio_set(dev, offset, value);
495 static int armada_37xx_gpio_probe(struct udevice *dev)
497 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
498 struct gpio_dev_priv *uc_priv;
500 uc_priv = dev_get_uclass_priv(dev);
501 uc_priv->bank_name = info->data->name;
502 uc_priv->gpio_count = info->data->nr_pins;
507 static const struct dm_gpio_ops armada_37xx_gpio_ops = {
508 .set_value = armada_37xx_gpio_set,
509 .get_value = armada_37xx_gpio_get,
510 .get_function = armada_37xx_gpio_get_direction,
511 .direction_input = armada_37xx_gpio_direction_input,
512 .direction_output = armada_37xx_gpio_direction_output,
515 static struct driver armada_37xx_gpio_driver = {
516 .name = "armada-37xx-gpio",
518 .probe = armada_37xx_gpio_probe,
519 .ops = &armada_37xx_gpio_ops,
522 static int armada_37xx_gpiochip_register(struct udevice *parent,
523 struct armada_37xx_pinctrl *info)
525 const void *blob = gd->fdt_blob;
526 int node = dev_of_offset(parent);
527 struct uclass_driver *drv;
533 /* Lookup GPIO driver */
534 drv = lists_uclass_lookup(UCLASS_GPIO);
536 puts("Cannot find GPIO driver\n");
540 fdt_for_each_subnode(subnode, blob, node) {
541 if (!fdtdec_get_bool(blob, subnode, "gpio-controller")) {
549 name = calloc(1, 32);
550 sprintf(name, "armada-37xx-gpio");
552 /* Create child device UCLASS_GPIO and bind it */
553 device_bind(parent, &armada_37xx_gpio_driver, name, NULL, subnode,
555 dev_set_of_offset(dev, subnode);
560 const struct pinctrl_ops armada_37xx_pinctrl_ops = {
561 .get_groups_count = armada_37xx_pmx_get_groups_count,
562 .get_group_name = armada_37xx_pmx_get_group_name,
563 .get_functions_count = armada_37xx_pmx_get_funcs_count,
564 .get_function_name = armada_37xx_pmx_get_func_name,
565 .pinmux_group_set = armada_37xx_pmx_group_set,
566 .set_state = pinctrl_generic_set_state,
569 int armada_37xx_pinctrl_probe(struct udevice *dev)
571 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
572 const struct armada_37xx_pin_data *pin_data;
575 info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
576 pin_data = info->data;
578 info->base = (void __iomem *)dev_get_addr(dev);
580 error("unable to find regmap\n");
584 info->groups = pin_data->groups;
585 info->ngroups = pin_data->ngroups;
588 * we allocate functions for number of pins and hope there are
589 * fewer unique functions than pins available
591 info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
592 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
597 ret = armada_37xx_fill_group(info);
601 ret = armada_37xx_fill_func(info);
605 ret = armada_37xx_gpiochip_register(dev, info);
612 static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
614 .compatible = "marvell,armada3710-sb-pinctrl",
615 .data = (ulong)&armada_37xx_pin_sb,
618 .compatible = "marvell,armada3710-nb-pinctrl",
619 .data = (ulong)&armada_37xx_pin_nb,
624 U_BOOT_DRIVER(armada_37xx_pinctrl) = {
625 .name = "armada-37xx-pinctrl",
626 .id = UCLASS_PINCTRL,
627 .of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
628 .probe = armada_37xx_pinctrl_probe,
629 .priv_auto_alloc_size = sizeof(struct armada_37xx_pinctrl),
630 .ops = &armada_37xx_pinctrl_ops,