1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
10 #include <dm/pinctrl.h>
11 #include <linux/bitops.h>
14 #include "pinctrl-mtmips-common.h"
16 DECLARE_GLOBAL_DATA_PTR;
19 #define GPIOMODE1_OFS 0x24
20 #define GPIOMODE2_OFS 0x28
22 #define EPHY4_1_PAD_SHIFT 17
23 #define EPHY4_1_PAD_MASK 0x0f
24 #define EPHY0_SHIFT 16
25 #define RF_OLT_MODE_SHIFT 12
26 #define N9_EINT_SRC_SHIFT 9
27 #define WLED_OD_SHIFT 8
28 #define REF_CLKO_PAD_SHIFT 4
29 #define I2S_CLK_PAD_SHIFT 3
30 #define I2S_WS_PAD_SHIFT 2
31 #define I2S_SDO_PAD_SHIFT 1
32 #define I2S_SDI_PAD_SHIFT 0
36 #define P4LED_K_SHIFT 26
37 #define P3LED_K_SHIFT 24
38 #define P2LED_K_SHIFT 22
39 #define P1LED_K_SHIFT 20
40 #define P0LED_K_SHIFT 18
41 #define WLED_K_SHIFT 16
42 #define P4LED_A_SHIFT 10
43 #define P3LED_A_SHIFT 8
44 #define P2LED_A_SHIFT 6
45 #define P1LED_A_SHIFT 4
46 #define P0LED_A_SHIFT 2
47 #define WLED_A_SHIFT 0
51 #define UART2_SHIFT 26
52 #define UART1_SHIFT 24
54 #define REFCLK_SHIFT 18
55 #define PERST_SHIFT 16
59 #define SDMODE_SHIFT 10
62 #define SPI_CS1_SHIFT 4
66 #define PAD_PU_G0_REG 0x00
67 #define PAD_PU_G1_REG 0x04
68 #define PAD_PD_G0_REG 0x10
69 #define PAD_PD_G1_REG 0x14
70 #define PAD_SR_G0_REG 0x20
71 #define PAD_SR_G1_REG 0x24
72 #define PAD_SMT_G0_REG 0x30
73 #define PAD_SMT_G1_REG 0x34
74 #define PAD_E2_G0_REG 0x40
75 #define PAD_E2_G1_REG 0x44
76 #define PAD_E4_G0_REG 0x50
77 #define PAD_E4_G1_REG 0x54
78 #define PAD_E8_G0_REG 0x60
79 #define PAD_E8_G1_REG 0x64
81 #define PIN_CONFIG_DRIVE_STRENGTH_28 (PIN_CONFIG_END + 1)
82 #define PIN_CONFIG_DRIVE_STRENGTH_4G (PIN_CONFIG_END + 2)
84 struct mt7628_pinctrl_priv {
85 struct mtmips_pinctrl_priv mp;
90 #if CONFIG_IS_ENABLED(PINMUX)
91 static const struct mtmips_pmx_func ephy4_1_pad_grp[] = {
96 static const struct mtmips_pmx_func ephy0_grp[] = {
101 static const struct mtmips_pmx_func rf_olt_grp[] = {
106 static const struct mtmips_pmx_func n9_eint_src_grp[] = {
111 static const struct mtmips_pmx_func wlen_od_grp[] = {
116 static const struct mtmips_pmx_func ref_clko_grp[] = {
121 static const struct mtmips_pmx_func i2s_clk_grp[] = {
126 static const struct mtmips_pmx_func i2s_ws_grp[] = {
131 static const struct mtmips_pmx_func i2s_sdo_grp[] = {
136 static const struct mtmips_pmx_func i2s_sdi_grp[] = {
141 static const struct mtmips_pmx_func pwm1_grp[] = {
148 static const struct mtmips_pmx_func pwm0_grp[] = {
155 static const struct mtmips_pmx_func uart2_grp[] = {
156 FUNC("sdxc d5 d4", 3),
162 static const struct mtmips_pmx_func uart1_grp[] = {
169 static const struct mtmips_pmx_func i2c_grp[] = {
176 static const struct mtmips_pmx_func refclk_grp[] = {
181 static const struct mtmips_pmx_func perst_grp[] = {
186 static const struct mtmips_pmx_func esd_grp[] = {
191 static const struct mtmips_pmx_func wdt_grp[] = {
196 static const struct mtmips_pmx_func spi_grp[] = {
201 static const struct mtmips_pmx_func sd_mode_grp[] = {
208 static const struct mtmips_pmx_func uart0_grp[] = {
215 static const struct mtmips_pmx_func i2s_grp[] = {
222 static const struct mtmips_pmx_func spi_cs1_grp[] = {
229 static const struct mtmips_pmx_func spis_grp[] = {
230 FUNC("pwm_uart2", 3),
236 static const struct mtmips_pmx_func gpio0_grp[] = {
243 static const struct mtmips_pmx_func wled_a_grp[] = {
250 static const struct mtmips_pmx_func p0led_a_grp[] = {
257 static const struct mtmips_pmx_func p1led_a_grp[] = {
264 static const struct mtmips_pmx_func p2led_a_grp[] = {
271 static const struct mtmips_pmx_func p3led_a_grp[] = {
278 static const struct mtmips_pmx_func p4led_a_grp[] = {
285 static const struct mtmips_pmx_func wled_k_grp[] = {
292 static const struct mtmips_pmx_func p0led_k_grp[] = {
299 static const struct mtmips_pmx_func p1led_k_grp[] = {
306 static const struct mtmips_pmx_func p2led_k_grp[] = {
313 static const struct mtmips_pmx_func p3led_k_grp[] = {
320 static const struct mtmips_pmx_func p4led_k_grp[] = {
327 static const struct mtmips_pmx_group mt7628_pinmux_data[] = {
328 GRP("ephy4_1_pad", ephy4_1_pad_grp, AGPIO_OFS, EPHY4_1_PAD_SHIFT,
330 GRP("ephy0", ephy0_grp, AGPIO_OFS, EPHY0_SHIFT, 1),
331 GRP("rf_olt", rf_olt_grp, AGPIO_OFS, RF_OLT_MODE_SHIFT, 1),
332 GRP("n9_eint_src", n9_eint_src_grp, AGPIO_OFS, N9_EINT_SRC_SHIFT, 1),
333 GRP("wlen_od", wlen_od_grp, AGPIO_OFS, WLED_OD_SHIFT, 1),
334 GRP("ref_clko_pad", ref_clko_grp, AGPIO_OFS, REF_CLKO_PAD_SHIFT, 1),
335 GRP("i2s_clk_pad", i2s_clk_grp, AGPIO_OFS, I2S_CLK_PAD_SHIFT, 1),
336 GRP("i2s_ws_pad", i2s_ws_grp, AGPIO_OFS, I2S_WS_PAD_SHIFT, 1),
337 GRP("i2s_sdo_pad", i2s_sdo_grp, AGPIO_OFS, I2S_SDO_PAD_SHIFT, 1),
338 GRP("i2s_sdi_pad", i2s_sdi_grp, AGPIO_OFS, I2S_SDI_PAD_SHIFT, 1),
339 GRP("pwm1", pwm1_grp, GPIOMODE1_OFS, PWM1_SHIFT, GM4_MASK),
340 GRP("pwm0", pwm0_grp, GPIOMODE1_OFS, PWM0_SHIFT, GM4_MASK),
341 GRP("uart2", uart2_grp, GPIOMODE1_OFS, UART2_SHIFT, GM4_MASK),
342 GRP("uart1", uart1_grp, GPIOMODE1_OFS, UART1_SHIFT, GM4_MASK),
343 GRP("i2c", i2c_grp, GPIOMODE1_OFS, I2C_SHIFT, GM4_MASK),
344 GRP("refclk", refclk_grp, GPIOMODE1_OFS, REFCLK_SHIFT, 1),
345 GRP("perst", perst_grp, GPIOMODE1_OFS, PERST_SHIFT, 1),
346 GRP("sd router", esd_grp, GPIOMODE1_OFS, ESD_SHIFT, 1),
347 GRP("wdt", wdt_grp, GPIOMODE1_OFS, WDT_SHIFT, 1),
348 GRP("spi", spi_grp, GPIOMODE1_OFS, SPI_SHIFT, 1),
349 GRP("sdmode", sd_mode_grp, GPIOMODE1_OFS, SDMODE_SHIFT, GM4_MASK),
350 GRP("uart0", uart0_grp, GPIOMODE1_OFS, UART0_SHIFT, GM4_MASK),
351 GRP("i2s", i2s_grp, GPIOMODE1_OFS, I2S_SHIFT, GM4_MASK),
352 GRP("spi cs1", spi_cs1_grp, GPIOMODE1_OFS, SPI_CS1_SHIFT, GM4_MASK),
353 GRP("spis", spis_grp, GPIOMODE1_OFS, SPIS_SHIFT, GM4_MASK),
354 GRP("gpio0", gpio0_grp, GPIOMODE1_OFS, GPIO0_SHIFT, GM4_MASK),
355 GRP("wled_a", wled_a_grp, GPIOMODE2_OFS, WLED_A_SHIFT, GM4_MASK),
356 GRP("p0led_a", p0led_a_grp, GPIOMODE2_OFS, P0LED_A_SHIFT, GM4_MASK),
357 GRP("p1led_a", p1led_a_grp, GPIOMODE2_OFS, P1LED_A_SHIFT, GM4_MASK),
358 GRP("p2led_a", p2led_a_grp, GPIOMODE2_OFS, P2LED_A_SHIFT, GM4_MASK),
359 GRP("p3led_a", p3led_a_grp, GPIOMODE2_OFS, P3LED_A_SHIFT, GM4_MASK),
360 GRP("p4led_a", p4led_a_grp, GPIOMODE2_OFS, P4LED_A_SHIFT, GM4_MASK),
361 GRP("wled_k", wled_k_grp, GPIOMODE2_OFS, WLED_K_SHIFT, GM4_MASK),
362 GRP("p0led_k", p0led_k_grp, GPIOMODE2_OFS, P0LED_K_SHIFT, GM4_MASK),
363 GRP("p1led_k", p1led_k_grp, GPIOMODE2_OFS, P1LED_K_SHIFT, GM4_MASK),
364 GRP("p2led_k", p2led_k_grp, GPIOMODE2_OFS, P2LED_K_SHIFT, GM4_MASK),
365 GRP("p3led_k", p3led_k_grp, GPIOMODE2_OFS, P3LED_K_SHIFT, GM4_MASK),
366 GRP("p4led_k", p4led_k_grp, GPIOMODE2_OFS, P4LED_K_SHIFT, GM4_MASK),
369 static int mt7628_get_groups_count(struct udevice *dev)
371 return ARRAY_SIZE(mt7628_pinmux_data);
374 static const char *mt7628_get_group_name(struct udevice *dev,
375 unsigned int selector)
377 return mt7628_pinmux_data[selector].name;
379 #endif /* CONFIG_IS_ENABLED(PINMUX) */
381 #if CONFIG_IS_ENABLED(PINCONF)
382 static const struct pinconf_param mt7628_conf_params[] = {
383 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
384 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
385 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
386 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
387 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
388 { "drive-strength-28", PIN_CONFIG_DRIVE_STRENGTH_28, 0 },
389 { "drive-strength-4g", PIN_CONFIG_DRIVE_STRENGTH_4G, 0 },
390 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
393 static const char *const mt7628_pins[] = {
443 static const u32 mt7628_drv_strength_28_tbl[] = {2, 4, 6, 8};
444 static const u32 mt7628_drv_strength_4g_tbl[] = {4, 8, 12, 16};
446 static int mt7628_set_drv_strength(void __iomem *base, u32 val, u32 bit,
447 const u32 tbl[], u32 reg_lo, u32 reg_hi)
451 for (i = 0; i < 4; i++)
458 clrsetbits_32(base + reg_lo, BIT(bit), (i & 1) << bit);
459 clrsetbits_32(base + reg_hi, BIT(bit), ((i >> 1) & 1) << bit);
464 static int mt7628_get_pins_count(struct udevice *dev)
466 return ARRAY_SIZE(mt7628_pins);
469 static const char *mt7628_get_pin_name(struct udevice *dev,
470 unsigned int selector)
472 return mt7628_pins[selector];
475 static int mt7628_pinconf_set(struct udevice *dev, unsigned int pin_selector,
476 unsigned int param, unsigned int argument)
478 struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);
482 offs = (pin_selector / 32) * 4;
483 bit = pin_selector % 32;
486 case PIN_CONFIG_BIAS_DISABLE:
487 clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
488 clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
490 case PIN_CONFIG_BIAS_PULL_UP:
491 setbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
492 clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
494 case PIN_CONFIG_BIAS_PULL_DOWN:
495 clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
496 setbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
498 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
499 clrsetbits_32(priv->pcbase + offs + PAD_SMT_G0_REG,
500 BIT(bit), (!!argument) << bit);
502 case PIN_CONFIG_DRIVE_STRENGTH_28:
503 ret = mt7628_set_drv_strength(priv->pcbase + offs, argument,
504 bit, mt7628_drv_strength_28_tbl,
505 PAD_E2_G0_REG, PAD_E4_G0_REG);
507 case PIN_CONFIG_DRIVE_STRENGTH_4G:
508 ret = mt7628_set_drv_strength(priv->pcbase + offs, argument,
509 bit, mt7628_drv_strength_4g_tbl,
510 PAD_E4_G0_REG, PAD_E8_G0_REG);
512 case PIN_CONFIG_SLEW_RATE:
513 clrsetbits_32(priv->pcbase + offs + PAD_SR_G0_REG,
514 BIT(bit), (!!argument) << bit);
524 static int mt7628_pinctrl_probe(struct udevice *dev)
526 struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);
529 #if CONFIG_IS_ENABLED(PINMUX)
530 ret = mtmips_pinctrl_probe(&priv->mp, ARRAY_SIZE(mt7628_pinmux_data),
532 #endif /* CONFIG_IS_ENABLED(PINMUX) */
537 static int mt7628_pinctrl_ofdata_to_platdata(struct udevice *dev)
539 struct mt7628_pinctrl_priv *priv = dev_get_priv(dev);
541 priv->mp.base = (void __iomem *)dev_remap_addr_index(dev, 0);
546 priv->pcbase = (void __iomem *)dev_remap_addr_index(dev, 1);
554 static const struct pinctrl_ops mt7628_pinctrl_ops = {
555 #if CONFIG_IS_ENABLED(PINMUX)
556 .get_groups_count = mt7628_get_groups_count,
557 .get_group_name = mt7628_get_group_name,
558 .get_functions_count = mtmips_get_functions_count,
559 .get_function_name = mtmips_get_function_name,
560 .pinmux_group_set = mtmips_pinmux_group_set,
561 #endif /* CONFIG_IS_ENABLED(PINMUX) */
562 #if CONFIG_IS_ENABLED(PINCONF)
563 .pinconf_num_params = ARRAY_SIZE(mt7628_conf_params),
564 .pinconf_params = mt7628_conf_params,
565 .get_pins_count = mt7628_get_pins_count,
566 .get_pin_name = mt7628_get_pin_name,
567 .pinconf_set = mt7628_pinconf_set,
568 #endif /* CONFIG_IS_ENABLED(PINCONF) */
569 .set_state = pinctrl_generic_set_state,
572 static const struct udevice_id mt7628_pinctrl_ids[] = {
573 { .compatible = "mediatek,mt7628-pinctrl" },
577 U_BOOT_DRIVER(mt7628_pinctrl) = {
578 .name = "mt7628-pinctrl",
579 .id = UCLASS_PINCTRL,
580 .of_match = mt7628_pinctrl_ids,
581 .ofdata_to_platdata = mt7628_pinctrl_ofdata_to_platdata,
582 .ops = &mt7628_pinctrl_ops,
583 .probe = mt7628_pinctrl_probe,
584 .priv_auto_alloc_size = sizeof(struct mt7628_pinctrl_priv),