1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi SoCs pinctrl driver
5 * Author: <horatiu.vultur@microchip.com>
6 * Copyright (c) 2019 Microsemi Corporation
12 #include <dm/device-internal.h>
14 #include <dm/pinctrl.h>
20 #include <asm/system.h>
21 #include "mscc-common.h"
60 static char * const serval_function_names[] = {
65 [FUNC_MIIM1] = "miim1",
66 [FUNC_PCI_WAKE] = "pci_wake",
72 [FUNC_RECO_CLK0] = "reco_clk0",
73 [FUNC_RECO_CLK1] = "reco_clk1",
84 [FUNC_SFP10] = "sfp10",
87 [FUNC_TACHO] = "tacho",
89 [FUNC_TWI_SCL_M] = "twi_scl_m",
91 [FUNC_UART2] = "uart2",
93 [FUNC_PTP1588] = "1588",
96 MSCC_P(0, SIO, NONE, NONE);
97 MSCC_P(1, SIO, NONE, NONE);
98 MSCC_P(2, SIO, NONE, NONE);
99 MSCC_P(3, SIO, NONE, NONE);
100 MSCC_P(4, TACHO, NONE, NONE);
101 MSCC_P(5, PWM, NONE, NONE);
102 MSCC_P(6, TWI, NONE, NONE);
103 MSCC_P(7, TWI, NONE, NONE);
104 MSCC_P(8, SI, NONE, NONE);
105 MSCC_P(9, SI, MD, NONE);
106 MSCC_P(10, SI, MD, NONE);
107 MSCC_P(11, SFP0, MD, TWI_SCL_M);
108 MSCC_P(12, SFP1, MD, TWI_SCL_M);
109 MSCC_P(13, SFP2, UART2, TWI_SCL_M);
110 MSCC_P(14, SFP3, UART2, TWI_SCL_M);
111 MSCC_P(15, SFP4, PTP1588, TWI_SCL_M);
112 MSCC_P(16, SFP5, PTP1588, TWI_SCL_M);
113 MSCC_P(17, SFP6, PCI_WAKE, TWI_SCL_M);
114 MSCC_P(18, SFP7, NONE, TWI_SCL_M);
115 MSCC_P(19, SFP8, NONE, TWI_SCL_M);
116 MSCC_P(20, SFP9, NONE, TWI_SCL_M);
117 MSCC_P(21, SFP10, NONE, TWI_SCL_M);
118 MSCC_P(22, NONE, NONE, NONE);
119 MSCC_P(23, NONE, NONE, NONE);
120 MSCC_P(24, NONE, NONE, NONE);
121 MSCC_P(25, NONE, NONE, NONE);
122 MSCC_P(26, UART, NONE, NONE);
123 MSCC_P(27, UART, NONE, NONE);
124 MSCC_P(28, IRQ0, NONE, NONE);
125 MSCC_P(29, IRQ1, NONE, NONE);
126 MSCC_P(30, PTP1588, NONE, NONE);
127 MSCC_P(31, PTP1588, NONE, NONE);
129 #define SERVAL_PIN(n) { \
131 .drv_data = &mscc_pin_##n \
134 static const struct mscc_pin_data serval_pins[] = {
169 static const unsigned long serval_gpios[] = {
170 [MSCC_GPIO_OUT_SET] = 0x00,
171 [MSCC_GPIO_OUT_CLR] = 0x04,
172 [MSCC_GPIO_OUT] = 0x08,
173 [MSCC_GPIO_IN] = 0x0c,
174 [MSCC_GPIO_OE] = 0x10,
175 [MSCC_GPIO_INTR] = 0x14,
176 [MSCC_GPIO_INTR_ENA] = 0x18,
177 [MSCC_GPIO_INTR_IDENT] = 0x1c,
178 [MSCC_GPIO_ALT0] = 0x20,
179 [MSCC_GPIO_ALT1] = 0x24,
182 static int serval_gpio_probe(struct udevice *dev)
184 struct gpio_dev_priv *uc_priv;
186 uc_priv = dev_get_uclass_priv(dev);
187 uc_priv->bank_name = "serval-gpio";
188 uc_priv->gpio_count = ARRAY_SIZE(serval_pins);
193 static struct driver serval_gpio_driver = {
194 .name = "serval-gpio",
196 .probe = serval_gpio_probe,
197 .ops = &mscc_gpio_ops,
200 static int serval_pinctrl_probe(struct udevice *dev)
204 ret = mscc_pinctrl_probe(dev, FUNC_MAX, serval_pins,
205 ARRAY_SIZE(serval_pins),
206 serval_function_names,
212 ret = device_bind(dev, &serval_gpio_driver, "serval-gpio", NULL,
213 dev_of_offset(dev), NULL);
221 static const struct udevice_id serval_pinctrl_of_match[] = {
222 { .compatible = "mscc,serval-pinctrl" },
226 U_BOOT_DRIVER(serval_pinctrl) = {
227 .name = "serval-pinctrl",
228 .id = UCLASS_PINCTRL,
229 .of_match = of_match_ptr(serval_pinctrl_of_match),
230 .probe = serval_pinctrl_probe,
231 .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
232 .ops = &mscc_pinctrl_ops,