1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi SoCs pinctrl driver
5 * Author: <alexandre.belloni@free-electrons.com>
6 * Author: <gregory.clement@bootlin.com>
7 * License: Dual MIT/GPL
8 * Copyright (c) 2017 Microsemi Corporation
12 #include <asm/system.h>
16 #include <dm/device-internal.h>
18 #include <dm/pinctrl.h>
23 #include "mscc-common.h"
57 static char * const ocelot_function_names[] = {
60 [FUNC_IRQ0_IN] = "irq0_in",
61 [FUNC_IRQ0_OUT] = "irq0_out",
62 [FUNC_IRQ1_IN] = "irq1_in",
63 [FUNC_IRQ1_OUT] = "irq1_out",
64 [FUNC_MIIM1] = "miim1",
65 [FUNC_PCI_WAKE] = "pci_wake",
71 [FUNC_RECO_CLK0] = "reco_clk0",
72 [FUNC_RECO_CLK1] = "reco_clk1",
81 [FUNC_TACHO] = "tacho",
83 [FUNC_TWI_SCL_M] = "twi_scl_m",
85 [FUNC_UART2] = "uart2",
88 MSCC_P(0, SG0, NONE, NONE);
89 MSCC_P(1, SG0, NONE, NONE);
90 MSCC_P(2, SG0, NONE, NONE);
91 MSCC_P(3, SG0, NONE, NONE);
92 MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI);
93 MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
94 MSCC_P(6, UART, TWI_SCL_M, NONE);
95 MSCC_P(7, UART, TWI_SCL_M, NONE);
96 MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT);
97 MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT);
98 MSCC_P(10, PTP2, TWI_SCL_M, SFP0);
99 MSCC_P(11, PTP3, TWI_SCL_M, SFP1);
100 MSCC_P(12, UART2, TWI_SCL_M, SFP2);
101 MSCC_P(13, UART2, TWI_SCL_M, SFP3);
102 MSCC_P(14, MIIM1, TWI_SCL_M, SFP4);
103 MSCC_P(15, MIIM1, TWI_SCL_M, SFP5);
104 MSCC_P(16, TWI, NONE, SI);
105 MSCC_P(17, TWI, TWI_SCL_M, SI);
106 MSCC_P(18, PTP0, TWI_SCL_M, NONE);
107 MSCC_P(19, PTP1, TWI_SCL_M, NONE);
108 MSCC_P(20, RECO_CLK0, TACHO, NONE);
109 MSCC_P(21, RECO_CLK1, PWM, NONE);
111 #define OCELOT_PIN(n) { \
113 .drv_data = &mscc_pin_##n \
116 static const struct mscc_pin_data ocelot_pins[] = {
141 static const unsigned long ocelot_gpios[] = {
142 [MSCC_GPIO_OUT_SET] = 0x00,
143 [MSCC_GPIO_OUT_CLR] = 0x04,
144 [MSCC_GPIO_OUT] = 0x08,
145 [MSCC_GPIO_IN] = 0x0c,
146 [MSCC_GPIO_OE] = 0x10,
147 [MSCC_GPIO_INTR] = 0x14,
148 [MSCC_GPIO_INTR_ENA] = 0x18,
149 [MSCC_GPIO_INTR_IDENT] = 0x1c,
150 [MSCC_GPIO_ALT0] = 0x20,
151 [MSCC_GPIO_ALT1] = 0x24,
154 static int ocelot_gpio_probe(struct udevice *dev)
156 struct gpio_dev_priv *uc_priv;
158 uc_priv = dev_get_uclass_priv(dev);
159 uc_priv->bank_name = "ocelot-gpio";
160 uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins);
165 static struct driver ocelot_gpio_driver = {
166 .name = "ocelot-gpio",
168 .probe = ocelot_gpio_probe,
169 .ops = &mscc_gpio_ops,
172 int ocelot_pinctrl_probe(struct udevice *dev)
176 ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
177 ARRAY_SIZE(ocelot_pins),
178 ocelot_function_names,
184 ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL,
185 dev_of_offset(dev), NULL);
190 static const struct udevice_id ocelot_pinctrl_of_match[] = {
191 {.compatible = "mscc,ocelot-pinctrl"},
195 U_BOOT_DRIVER(ocelot_pinctrl) = {
196 .name = "ocelot-pinctrl",
197 .id = UCLASS_PINCTRL,
198 .of_match = of_match_ptr(ocelot_pinctrl_of_match),
199 .probe = ocelot_pinctrl_probe,
200 .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
201 .ops = &mscc_pinctrl_ops,