common: Drop image.h from common header
[oweals/u-boot.git] / drivers / pinctrl / meson / pinctrl-meson.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
4  */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <malloc.h>
9 #include <dm/device-internal.h>
10 #include <dm/device_compat.h>
11 #include <dm/lists.h>
12 #include <dm/pinctrl.h>
13 #include <fdt_support.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/libfdt.h>
17 #include <linux/sizes.h>
18 #include <asm/gpio.h>
19
20 #include "pinctrl-meson.h"
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 static const char *meson_pinctrl_dummy_name = "_dummy";
25
26 static char pin_name[PINNAME_SIZE];
27
28 int meson_pinctrl_get_groups_count(struct udevice *dev)
29 {
30         struct meson_pinctrl *priv = dev_get_priv(dev);
31
32         return priv->data->num_groups;
33 }
34
35 const char *meson_pinctrl_get_group_name(struct udevice *dev,
36                                          unsigned int selector)
37 {
38         struct meson_pinctrl *priv = dev_get_priv(dev);
39
40         if (!priv->data->groups[selector].name)
41                 return meson_pinctrl_dummy_name;
42
43         return priv->data->groups[selector].name;
44 }
45
46 int meson_pinctrl_get_pins_count(struct udevice *dev)
47 {
48         struct meson_pinctrl *priv = dev_get_priv(dev);
49
50         return priv->data->num_pins;
51 }
52
53 const char *meson_pinctrl_get_pin_name(struct udevice *dev,
54                                        unsigned int selector)
55 {
56         struct meson_pinctrl *priv = dev_get_priv(dev);
57
58         if (selector > priv->data->num_pins ||
59             selector > priv->data->funcs[0].num_groups)
60                 snprintf(pin_name, PINNAME_SIZE, "Error");
61         else
62                 snprintf(pin_name, PINNAME_SIZE, "%s",
63                          priv->data->funcs[0].groups[selector]);
64
65         return pin_name;
66 }
67
68 int meson_pinmux_get_functions_count(struct udevice *dev)
69 {
70         struct meson_pinctrl *priv = dev_get_priv(dev);
71
72         return priv->data->num_funcs;
73 }
74
75 const char *meson_pinmux_get_function_name(struct udevice *dev,
76                                            unsigned int selector)
77 {
78         struct meson_pinctrl *priv = dev_get_priv(dev);
79
80         return priv->data->funcs[selector].name;
81 }
82
83 static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
84                                        enum meson_reg_type reg_type,
85                                        unsigned int *reg, unsigned int *bit)
86 {
87         struct meson_pinctrl *priv = dev_get_priv(dev);
88         struct meson_bank *bank = NULL;
89         struct meson_reg_desc *desc;
90         unsigned int pin;
91         int i;
92
93         pin = priv->data->pin_base + offset;
94
95         for (i = 0; i < priv->data->num_banks; i++) {
96                 if (pin >= priv->data->banks[i].first &&
97                     pin <= priv->data->banks[i].last) {
98                         bank = &priv->data->banks[i];
99                         break;
100                 }
101         }
102
103         if (!bank)
104                 return -EINVAL;
105
106         desc = &bank->regs[reg_type];
107         *reg = desc->reg * 4;
108         *bit = desc->bit + pin - bank->first;
109
110         return 0;
111 }
112
113 int meson_gpio_get(struct udevice *dev, unsigned int offset)
114 {
115         struct meson_pinctrl *priv = dev_get_priv(dev->parent);
116         unsigned int reg, bit;
117         int ret;
118
119         ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_IN, &reg,
120                                           &bit);
121         if (ret)
122                 return ret;
123
124         return !!(readl(priv->reg_gpio + reg) & BIT(bit));
125 }
126
127 int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
128 {
129         struct meson_pinctrl *priv = dev_get_priv(dev->parent);
130         unsigned int reg, bit;
131         int ret;
132
133         ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_OUT, &reg,
134                                           &bit);
135         if (ret)
136                 return ret;
137
138         clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
139
140         return 0;
141 }
142
143 int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
144 {
145         struct meson_pinctrl *priv = dev_get_priv(dev->parent);
146         unsigned int reg, bit, val;
147         int ret;
148
149         ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, &reg,
150                                           &bit);
151         if (ret)
152                 return ret;
153
154         val = readl(priv->reg_gpio + reg);
155
156         return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
157 }
158
159 int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
160 {
161         struct meson_pinctrl *priv = dev_get_priv(dev->parent);
162         unsigned int reg, bit;
163         int ret;
164
165         ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, &reg,
166                                           &bit);
167         if (ret)
168                 return ret;
169
170         setbits_le32(priv->reg_gpio + reg, BIT(bit));
171
172         return 0;
173 }
174
175 int meson_gpio_direction_output(struct udevice *dev,
176                                 unsigned int offset, int value)
177 {
178         struct meson_pinctrl *priv = dev_get_priv(dev->parent);
179         unsigned int reg, bit;
180         int ret;
181
182         ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, &reg,
183                                           &bit);
184         if (ret)
185                 return ret;
186
187         clrbits_le32(priv->reg_gpio + reg, BIT(bit));
188
189         ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_OUT, &reg,
190                                           &bit);
191         if (ret)
192                 return ret;
193
194         clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
195
196         return 0;
197 }
198
199 static int meson_pinconf_bias_set(struct udevice *dev, unsigned int pin,
200                                   unsigned int param)
201 {
202         struct meson_pinctrl *priv = dev_get_priv(dev);
203         unsigned int offset = pin - priv->data->pin_base;
204         unsigned int reg, bit;
205         int ret;
206
207         ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_PULLEN, &reg, &bit);
208         if (ret)
209                 return ret;
210
211         if (param == PIN_CONFIG_BIAS_DISABLE) {
212                 clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), 0);
213                 return 0;
214         }
215
216         /* othewise, enable the bias and select level */
217         clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), 1);
218         ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_PULL, &reg, &bit);
219         if (ret)
220                 return ret;
221
222         clrsetbits_le32(priv->reg_pull + reg, BIT(bit),
223                         param == PIN_CONFIG_BIAS_PULL_UP);
224
225         return 0;
226 }
227
228 static int meson_pinconf_drive_strength_set(struct udevice *dev,
229                                             unsigned int pin,
230                                             unsigned int drive_strength_ua)
231 {
232         struct meson_pinctrl *priv = dev_get_priv(dev);
233         unsigned int offset = pin - priv->data->pin_base;
234         unsigned int reg, bit;
235         unsigned int ds_val;
236         int ret;
237
238         if (!priv->reg_ds) {
239                 dev_err(dev, "drive-strength-microamp not supported\n");
240                 return -ENOTSUPP;
241         }
242
243         ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DS, &reg, &bit);
244         if (ret)
245                 return ret;
246
247         bit = bit << 1;
248
249         if (drive_strength_ua <= 500) {
250                 ds_val = MESON_PINCONF_DRV_500UA;
251         } else if (drive_strength_ua <= 2500) {
252                 ds_val = MESON_PINCONF_DRV_2500UA;
253         } else if (drive_strength_ua <= 3000) {
254                 ds_val = MESON_PINCONF_DRV_3000UA;
255         } else if (drive_strength_ua <= 4000) {
256                 ds_val = MESON_PINCONF_DRV_4000UA;
257         } else {
258                 dev_warn(dev,
259                          "pin %u: invalid drive-strength-microamp : %d , default to 4mA\n",
260                          pin, drive_strength_ua);
261                 ds_val = MESON_PINCONF_DRV_4000UA;
262         }
263
264         clrsetbits_le32(priv->reg_ds + reg, 0x3 << bit, ds_val << bit);
265
266         return 0;
267 }
268
269 int meson_pinconf_set(struct udevice *dev, unsigned int pin,
270                       unsigned int param, unsigned int arg)
271 {
272         int ret;
273
274         switch (param) {
275         case PIN_CONFIG_BIAS_DISABLE:
276         case PIN_CONFIG_BIAS_PULL_UP:
277         case PIN_CONFIG_BIAS_PULL_DOWN:
278                 ret = meson_pinconf_bias_set(dev, pin, param);
279                 break;
280         case PIN_CONFIG_DRIVE_STRENGTH_UA:
281                 ret = meson_pinconf_drive_strength_set(dev, pin, arg);
282                 break;
283         default:
284                 dev_err(dev, "unsupported configuration parameter %u\n", param);
285                 return -EINVAL;
286         }
287
288         return ret;
289 }
290
291 int meson_pinconf_group_set(struct udevice *dev,
292                             unsigned int group_selector,
293                             unsigned int param, unsigned int arg)
294 {
295         struct meson_pinctrl *priv = dev_get_priv(dev);
296         struct meson_pmx_group *grp = &priv->data->groups[group_selector];
297         int i, ret;
298
299         for (i = 0; i < grp->num_pins; i++) {
300                 ret = meson_pinconf_set(dev, grp->pins[i], param, arg);
301                 if (ret)
302                         return ret;
303         }
304
305         return 0;
306 }
307
308 int meson_gpio_probe(struct udevice *dev)
309 {
310         struct meson_pinctrl *priv = dev_get_priv(dev->parent);
311         struct gpio_dev_priv *uc_priv;
312
313         uc_priv = dev_get_uclass_priv(dev);
314         uc_priv->bank_name = priv->data->name;
315         uc_priv->gpio_count = priv->data->num_pins;
316
317         return 0;
318 }
319
320 static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
321 {
322         int index, len = 0;
323         const fdt32_t *reg;
324
325         index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", name);
326         if (index < 0)
327                 return FDT_ADDR_T_NONE;
328
329         reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
330         if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns))))
331                 return FDT_ADDR_T_NONE;
332
333         reg += index * (na + ns);
334
335         return fdt_translate_address((void *)gd->fdt_blob, offset, reg);
336 }
337
338 int meson_pinctrl_probe(struct udevice *dev)
339 {
340         struct meson_pinctrl *priv = dev_get_priv(dev);
341         struct uclass_driver *drv;
342         struct udevice *gpio_dev;
343         fdt_addr_t addr;
344         int node, gpio = -1, len;
345         int na, ns;
346         char *name;
347
348         na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
349         if (na < 1) {
350                 debug("bad #address-cells\n");
351                 return -EINVAL;
352         }
353
354         ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
355         if (ns < 1) {
356                 debug("bad #size-cells\n");
357                 return -EINVAL;
358         }
359
360         fdt_for_each_subnode(node, gd->fdt_blob, dev_of_offset(dev)) {
361                 if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
362                         gpio = node;
363                         break;
364                 }
365         }
366
367         if (!gpio) {
368                 debug("gpio node not found\n");
369                 return -EINVAL;
370         }
371
372         addr = parse_address(gpio, "mux", na, ns);
373         if (addr == FDT_ADDR_T_NONE) {
374                 debug("mux address not found\n");
375                 return -EINVAL;
376         }
377         priv->reg_mux = (void __iomem *)addr;
378
379         addr = parse_address(gpio, "gpio", na, ns);
380         if (addr == FDT_ADDR_T_NONE) {
381                 debug("gpio address not found\n");
382                 return -EINVAL;
383         }
384         priv->reg_gpio = (void __iomem *)addr;
385
386         addr = parse_address(gpio, "pull", na, ns);
387         /* Use gpio region if pull one is not present */
388         if (addr == FDT_ADDR_T_NONE)
389                 priv->reg_pull = priv->reg_gpio;
390         else
391                 priv->reg_pull = (void __iomem *)addr;
392
393         addr = parse_address(gpio, "pull-enable", na, ns);
394         /* Use pull region if pull-enable one is not present */
395         if (addr == FDT_ADDR_T_NONE)
396                 priv->reg_pullen = priv->reg_pull;
397         else
398                 priv->reg_pullen = (void __iomem *)addr;
399
400         addr = parse_address(gpio, "ds", na, ns);
401         /* Drive strength region is optional */
402         if (addr == FDT_ADDR_T_NONE)
403                 priv->reg_ds = NULL;
404         else
405                 priv->reg_ds = (void __iomem *)addr;
406
407         priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
408
409         /* Lookup GPIO driver */
410         drv = lists_uclass_lookup(UCLASS_GPIO);
411         if (!drv) {
412                 puts("Cannot find GPIO driver\n");
413                 return -ENOENT;
414         }
415
416         name = calloc(1, 32);
417         sprintf(name, "meson-gpio");
418
419         /* Create child device UCLASS_GPIO and bind it */
420         device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev);
421         dev_set_of_offset(gpio_dev, gpio);
422
423         return 0;
424 }