1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Sean Wang <sean.wang@mediatek.com>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/platform_device.h>
14 #include <linux/of_irq.h>
17 #include "pinctrl-mtk-common-v2.h"
20 * struct mtk_drive_desc - the structure that holds the information
21 * of the driving current
22 * @min: the minimum current of this group
23 * @max: the maximum current of this group
24 * @step: the step current of this group
25 * @scal: the weight factor
27 * formula: output = ((input) / step - 1) * scal
29 struct mtk_drive_desc {
36 /* The groups of drive strength */
37 static const struct mtk_drive_desc mtk_drive[] = {
38 [DRV_GRP0] = { 4, 16, 4, 1 },
39 [DRV_GRP1] = { 4, 16, 4, 2 },
40 [DRV_GRP2] = { 2, 8, 2, 1 },
41 [DRV_GRP3] = { 2, 8, 2, 2 },
42 [DRV_GRP4] = { 2, 16, 2, 1 },
45 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
47 writel_relaxed(val, pctl->base[i] + reg);
50 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
52 return readl_relaxed(pctl->base[i] + reg);
55 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
59 val = mtk_r32(pctl, i, reg);
62 mtk_w32(pctl, i, reg, val);
65 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
66 const struct mtk_pin_desc *desc,
67 int field, struct mtk_pin_field *pfd)
69 const struct mtk_pin_field_calc *c, *e;
70 const struct mtk_pin_reg_calc *rc;
73 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
74 rc = &hw->soc->reg_cal[field];
77 "Not support field %d for pin %d (%s)\n",
78 field, desc->number, desc->name);
86 if (desc->number >= c->s_pin && desc->number <= c->e_pin)
92 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
93 field, desc->number, desc->name);
97 if (c->i_base > hw->nbase - 1) {
99 "Invalid base for field %d for pin = %d (%s)\n",
100 field, desc->number, desc->name);
104 /* Calculated bits as the overall offset the pin is located at,
105 * if c->fixed is held, that determines the all the pins in the
106 * range use the same field with the s_pin.
108 bits = c->fixed ? c->s_bit : c->s_bit +
109 (desc->number - c->s_pin) * (c->x_bits);
111 /* Fill pfd from bits. For example 32-bit register applied is assumed
112 * when c->sz_reg is equal to 32.
114 pfd->index = c->i_base;
115 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
116 pfd->bitpos = bits % c->sz_reg;
117 pfd->mask = (1 << c->x_bits) - 1;
119 /* pfd->next is used for indicating that bit wrapping-around happens
120 * which requires the manipulation for bit 0 starting in the next
121 * register to form the complete field read/write.
123 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
128 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
129 const struct mtk_pin_desc *desc,
130 int field, struct mtk_pin_field *pfd)
132 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
133 dev_err(hw->dev, "Invalid Field %d\n", field);
137 return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
140 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
142 *l = 32 - pf->bitpos;
143 *h = get_count_order(pf->mask) - *l;
146 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
147 struct mtk_pin_field *pf, int value)
149 int nbits_l, nbits_h;
151 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
153 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
154 (value & pf->mask) << pf->bitpos);
156 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
157 (value & pf->mask) >> nbits_l);
160 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
161 struct mtk_pin_field *pf, int *value)
163 int nbits_l, nbits_h, h, l;
165 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
167 l = (mtk_r32(hw, pf->index, pf->offset)
168 >> pf->bitpos) & (BIT(nbits_l) - 1);
169 h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
170 & (BIT(nbits_h) - 1);
172 *value = (h << nbits_l) | l;
175 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
176 int field, int value)
178 struct mtk_pin_field pf;
181 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
186 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
187 (value & pf.mask) << pf.bitpos);
189 mtk_hw_write_cross_field(hw, &pf, value);
194 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
195 int field, int *value)
197 struct mtk_pin_field pf;
200 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
205 *value = (mtk_r32(hw, pf.index, pf.offset)
206 >> pf.bitpos) & pf.mask;
208 mtk_hw_read_cross_field(hw, &pf, value);
213 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
215 const struct mtk_pin_desc *desc;
218 desc = (const struct mtk_pin_desc *)hw->soc->pins;
220 while (i < hw->soc->npins) {
221 if (desc[i].eint.eint_n == eint_n)
222 return desc[i].number;
229 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
230 unsigned int *gpio_n,
231 struct gpio_chip **gpio_chip)
233 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
234 const struct mtk_pin_desc *desc;
236 desc = (const struct mtk_pin_desc *)hw->soc->pins;
237 *gpio_chip = &hw->chip;
239 /* Be greedy to guess first gpio_n is equal to eint_n */
240 if (desc[eint_n].eint.eint_n == eint_n)
243 *gpio_n = mtk_xt_find_eint_num(hw, eint_n);
245 return *gpio_n == EINT_NA ? -EINVAL : 0;
248 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
250 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
251 const struct mtk_pin_desc *desc;
252 struct gpio_chip *gpio_chip;
256 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
260 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
262 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
269 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
271 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
272 const struct mtk_pin_desc *desc;
273 struct gpio_chip *gpio_chip;
277 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
281 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
283 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
288 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
292 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
293 /* SMT is supposed to be supported by every real GPIO and doesn't
294 * support virtual GPIOs, so the extra condition err != -ENOTSUPP
295 * is just for adding EINT support to these virtual GPIOs. It should
296 * add an extra flag in the pin descriptor when more pins with
297 * distinctive characteristic come out.
299 if (err && err != -ENOTSUPP)
305 static const struct mtk_eint_xt mtk_eint_xt = {
306 .get_gpio_n = mtk_xt_get_gpio_n,
307 .get_gpio_state = mtk_xt_get_gpio_state,
308 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
311 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
313 struct device_node *np = pdev->dev.of_node;
314 struct resource *res;
316 if (!IS_ENABLED(CONFIG_EINT_MTK))
319 if (!of_property_read_bool(np, "interrupt-controller"))
322 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
326 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
328 dev_err(&pdev->dev, "Unable to get eint resource\n");
332 hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
333 if (IS_ERR(hw->eint->base))
334 return PTR_ERR(hw->eint->base);
336 hw->eint->irq = irq_of_parse_and_map(np, 0);
340 if (!hw->soc->eint_hw)
343 hw->eint->dev = &pdev->dev;
344 hw->eint->hw = hw->soc->eint_hw;
346 hw->eint->gpio_xlate = &mtk_eint_xt;
348 return mtk_eint_do_init(hw->eint);
352 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
353 const struct mtk_pin_desc *desc)
357 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
362 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
370 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
371 const struct mtk_pin_desc *desc, int *res)
376 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
380 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
384 if (v == MTK_ENABLE || v2 == MTK_ENABLE)
392 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
393 const struct mtk_pin_desc *desc, bool pullup)
397 arg = pullup ? 1 : 2;
399 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
403 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
411 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
412 const struct mtk_pin_desc *desc, bool pullup, int *res)
416 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
418 err = mtk_hw_get_value(hw, desc, reg, &v);
431 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
432 const struct mtk_pin_desc *desc)
436 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
444 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
445 const struct mtk_pin_desc *desc, int *res)
449 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
461 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
462 const struct mtk_pin_desc *desc, bool pullup)
466 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
468 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
473 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
480 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
481 const struct mtk_pin_desc *desc, bool pullup,
486 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
490 if (v == MTK_DISABLE)
493 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
497 if (pullup ^ (v == MTK_PULLUP))
506 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
507 const struct mtk_pin_desc *desc, u32 arg)
509 const struct mtk_drive_desc *tb;
512 tb = &mtk_drive[desc->drv_n];
513 /* 4mA when (e8, e4) = (0, 0)
514 * 8mA when (e8, e4) = (0, 1)
515 * 12mA when (e8, e4) = (1, 0)
516 * 16mA when (e8, e4) = (1, 1)
518 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
519 arg = (arg / tb->step - 1) * tb->scal;
520 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
525 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
534 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
535 const struct mtk_pin_desc *desc, int *val)
537 const struct mtk_drive_desc *tb;
540 tb = &mtk_drive[desc->drv_n];
542 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
546 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
550 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
551 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
553 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
559 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
560 const struct mtk_pin_desc *desc, u32 arg)
562 const struct mtk_drive_desc *tb;
565 tb = &mtk_drive[desc->drv_n];
567 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
568 arg = (arg / tb->step - 1) * tb->scal;
570 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
579 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
580 const struct mtk_pin_desc *desc, int *val)
582 const struct mtk_drive_desc *tb;
585 tb = &mtk_drive[desc->drv_n];
587 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
591 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
596 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
597 const struct mtk_pin_desc *desc, bool pullup,
602 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
603 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
604 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
605 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
607 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
611 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
616 arg = pullup ? 0 : 1;
618 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
620 /* If PUPD register is not supported for that pin, let's fallback to
621 * general bias control.
623 if (err == -ENOTSUPP) {
624 if (hw->soc->bias_set) {
625 err = hw->soc->bias_set(hw, desc, pullup);
636 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
637 const struct mtk_pin_desc *desc, bool pullup,
643 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
645 /* If PUPD register is not supported for that pin, let's fallback to
646 * general bias control.
648 if (err == -ENOTSUPP) {
649 if (hw->soc->bias_get) {
650 err = hw->soc->bias_get(hw, desc, pullup, val);
657 /* t == 0 supposes PULLUP for the customized PULL setup */
665 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
669 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
673 *val = (t | t2 << 1) & 0x7;
678 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
679 const struct mtk_pin_desc *desc, u32 arg)
683 int e0 = !!(arg & 2);
684 int e1 = !!(arg & 4);
686 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
693 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
697 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
704 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
705 const struct mtk_pin_desc *desc, u32 *val)
710 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
714 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
718 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
722 *val = (en | e0 << 1 | e1 << 2) & 0x7;