1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Exynos pinctrl driver header.
4 * Copyright (C) 2016 Samsung Electronics
5 * Thomas Abraham <thomas.ab@samsung.com>
8 #ifndef __PINCTRL_EXYNOS_H_
9 #define __PINCTRL_EXYNOS__H_
11 #define PIN_CON 0x00 /* Offset of pin function register */
12 #define PIN_DAT 0x04 /* Offset of pin data register */
13 #define PIN_PUD 0x08 /* Offset of pin pull up/down config register */
14 #define PIN_DRV 0x0C /* Offset of pin drive strength register */
17 * struct samsung_pin_bank_data: represent a controller pin-bank data.
18 * @offset: starting offset of the pin-bank registers.
19 * @nr_pins: number of pins included in this bank.
20 * @name: name to be prefixed for each pin in this pin bank.
22 struct samsung_pin_bank_data {
28 #define EXYNOS_PIN_BANK(pins, reg, id) \
36 * struct samsung_pin_ctrl: represent a pin controller.
37 * @pin_banks: list of pin banks included in this controller.
38 * @nr_banks: number of pin banks.
40 struct samsung_pin_ctrl {
41 const struct samsung_pin_bank_data *pin_banks;
46 * struct exynos_pinctrl_priv: exynos pin controller driver private data
47 * @pin_ctrl: pin controller bank information.
48 * @base: base address of the pin controller instance.
49 * @num_banks: number of pin banks included in the pin controller.
51 struct exynos_pinctrl_priv {
52 const struct samsung_pin_ctrl *pin_ctrl;
58 * struct exynos_pinctrl_config_data: configuration for a peripheral.
59 * @offset: offset of the config registers in the controller.
60 * @mask: value of the register to be masked with.
61 * @value: new value to be programmed.
63 struct exynos_pinctrl_config_data {
64 const unsigned int offset;
65 const unsigned int mask;
66 const unsigned int value;
70 void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
71 unsigned int num_conf, unsigned long base);
72 int exynos_pinctrl_set_state(struct udevice *dev,
73 struct udevice *config);
74 int exynos_pinctrl_probe(struct udevice *dev);
76 #endif /* __PINCTRL_EXYNOS_H_ */