drivers/phy/qualcomm/phy-qcom-qmp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #include "phy-qcom-qmp.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 #define REFCLK_DRV_DSBL                         BIT(1)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 #define PLL_READY_GATE_EN                       BIT(3)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
  39 #define PCS_READY                               BIT(0)
  40
  41 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  42 /* DP PHY soft reset */
  43 #define SW_DPPHY_RESET                          BIT(0)
  44 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  45 #define SW_DPPHY_RESET_MUX                      BIT(1)
  46 /* USB3 PHY soft reset */
  47 #define SW_USB3PHY_RESET                        BIT(2)
  48 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  49 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  50
  51 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  52 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  53 #define DP_MODE                                 BIT(1) /* enables DP mode */
  54
  55 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  56 #define ARCVR_DTCT_EN                           BIT(0)
  57 #define ALFPS_DTCT_EN                           BIT(1)
  58 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  59
  60 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  61 #define IRQ_CLEAR                               BIT(0)
  62
  63 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  64 #define RCVR_DETECT                             BIT(0)
  65
  66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  67 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  68
  69 #define PHY_INIT_COMPLETE_TIMEOUT               1000
  70 #define POWER_DOWN_DELAY_US_MIN                 10
  71 #define POWER_DOWN_DELAY_US_MAX                 11
  72
  73 #define MAX_PROP_NAME                           32
  74
  75 /* Define the assumed distance between lanes for underspecified device trees. */
  76 #define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  77
  78 struct qmp_phy_init_tbl {
  79         unsigned int offset;
  80         unsigned int val;
  81         /*
  82          * register part of layout ?
  83          * if yes, then offset gives index in the reg-layout
  84          */
  85         int in_layout;
  86 };
  87
  88 #define QMP_PHY_INIT_CFG(o, v)          \
  89         {                               \
  90                 .offset = o,            \
  91                 .val = v,               \
  92         }
  93
  94 #define QMP_PHY_INIT_CFG_L(o, v)        \
  95         {                               \
  96                 .offset = o,            \
  97                 .val = v,               \
  98                 .in_layout = 1,         \
  99         }
 100
 101 /* set of registers with offsets different per-PHY */
 102 enum qphy_reg_layout {
 103         /* Common block control registers */
 104         QPHY_COM_SW_RESET,
 105         QPHY_COM_POWER_DOWN_CONTROL,
 106         QPHY_COM_START_CONTROL,
 107         QPHY_COM_PCS_READY_STATUS,
 108         /* PCS registers */
 109         QPHY_PLL_LOCK_CHK_DLY_TIME,
 110         QPHY_FLL_CNTRL1,
 111         QPHY_FLL_CNTRL2,
 112         QPHY_FLL_CNT_VAL_L,
 113         QPHY_FLL_CNT_VAL_H_TOL,
 114         QPHY_FLL_MAN_CODE,
 115         QPHY_SW_RESET,
 116         QPHY_START_CTRL,
 117         QPHY_PCS_READY_STATUS,
 118         QPHY_PCS_STATUS,
 119         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 120         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 121         QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 122 };
 123
 124 static const unsigned int pciephy_regs_layout[] = {
 125         [QPHY_COM_SW_RESET]             = 0x400,
 126         [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 127         [QPHY_COM_START_CONTROL]        = 0x408,
 128         [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 129         [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 130         [QPHY_FLL_CNTRL1]               = 0xc4,
 131         [QPHY_FLL_CNTRL2]               = 0xc8,
 132         [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 133         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 134         [QPHY_FLL_MAN_CODE]             = 0xd4,
 135         [QPHY_SW_RESET]                 = 0x00,
 136         [QPHY_START_CTRL]               = 0x08,
 137         [QPHY_PCS_STATUS]               = 0x174,
 138 };
 139
 140 static const unsigned int usb3phy_regs_layout[] = {
 141         [QPHY_FLL_CNTRL1]               = 0xc0,
 142         [QPHY_FLL_CNTRL2]               = 0xc4,
 143         [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 144         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 145         [QPHY_FLL_MAN_CODE]             = 0xd0,
 146         [QPHY_SW_RESET]                 = 0x00,
 147         [QPHY_START_CTRL]               = 0x08,
 148         [QPHY_PCS_STATUS]               = 0x17c,
 149         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 150         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 151         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 152 };
 153
 154 static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
 155         [QPHY_SW_RESET]                 = 0x00,
 156         [QPHY_START_CTRL]               = 0x08,
 157         [QPHY_PCS_STATUS]               = 0x174,
 158         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 159         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 160         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 161 };
 162
 163 static const unsigned int sdm845_ufsphy_regs_layout[] = {
 164         [QPHY_START_CTRL]               = 0x00,
 165         [QPHY_PCS_READY_STATUS]         = 0x160,
 166 };
 167
 168 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 169         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 170         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 171         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 172         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 173         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 174         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 175         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 176         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 177         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 178         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 179         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 180         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 181         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 182         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 183         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 184         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 185         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 186         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 187         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 188         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 189         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 190         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 191         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 192         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 193         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 194         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 195         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 196         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 197         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 198         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 199         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 200         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 201         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 202         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 203         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 204         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 205         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 206         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 207         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 208         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 209         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 210         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 211         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 212 };
 213
 214 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 215         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 216         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 217 };
 218
 219 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 220         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 221         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 222         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 223         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 224         QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 225         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 226         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 227         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 228         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 229         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 230 };
 231
 232 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 233         QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 234         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 235         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 236
 237         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 238
 239         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 240         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 241         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 242         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 243         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 244 };
 245
 246 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
 247         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 248         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 249         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
 250         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 251         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 252         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 253         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 254         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 255         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 256         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 257         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 258         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 259         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 260         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 261         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 262         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 263         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 264         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 265         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 266         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 267         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 268         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 269         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 270         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 271         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 272         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 273         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 274         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 275         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 276         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 277         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 278         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 279         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 280         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 281         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 282         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 283         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 284         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 285         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 286         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 287         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 288         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 289 };
 290
 291 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 292         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 293         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 294         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 295         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 296 };
 297
 298 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 299         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 300         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 301         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 302         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 303         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 304         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 305         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 306         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 307         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 308         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 309         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 310         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 311         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 312         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 313 };
 314
 315 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 316         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 317         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 318         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 319         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 320         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 321         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 322         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 323         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 324         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 325         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 326 };
 327
 328 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 329         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 333         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 336         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 337         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 338         /* PLL and Loop filter settings */
 339         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 340         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 341         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 342         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 343         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 345         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 346         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 347         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 348         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 349         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 350         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 351         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 352         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 353         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 354         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 355         /* SSC settings */
 356         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 357         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 358         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 359         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 360         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 361         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 362         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 363 };
 364
 365 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 366         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 367         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 368         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 369 };
 370
 371 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 372         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 373         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 374         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 375         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 376         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 377         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 378         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 379         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 380         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 381         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 382 };
 383
 384 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 385         /* FLL settings */
 386         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 387         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 388         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 389         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 390         QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 391
 392         /* Lock Det settings */
 393         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 394         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 395         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 396         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 397 };
 398
 399 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 400         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 401         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 402         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 403         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 404         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 405         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
 406         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 407         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 408         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 409         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 410         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 411         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 412         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 413         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 414         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 415         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 416         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 417         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 418         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 419         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 420         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 421         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 422         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 423         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 424         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 425         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 426         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 427         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 428         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 429         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 430         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 431         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 432         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
 433         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 434         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 435         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 436         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 437         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 438         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 439         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 440         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 441         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
 442 };
 443
 444 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 445         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 446         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 447         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 448         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 449 };
 450
 451 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 452         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 453         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 454         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 455         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 456         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 457         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 458         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 459         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
 460 };
 461
 462 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 463         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 464         QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 465         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 466         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 467         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 468         QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 469         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 470         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 471         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 472         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 473         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 474         QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 475         QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 476 };
 477
 478 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 479         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 480         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 481         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 482         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 483         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 484         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 485         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 486         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 487         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 488         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 489         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 490         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 491         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 492         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 493         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 494         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 495         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 496         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 497         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 498         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 499         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 500         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 501         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 502         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 503         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 504         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 505         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 506         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 507         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 508         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 509         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 510         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 511         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 512         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 513         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 514         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 515 };
 516
 517 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 518         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 519         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 520         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 521         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 522         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 523 };
 524
 525 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 526         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 527         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 528         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 529         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 530         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 531         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 532         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 533         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 534         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 535 };
 536
 537 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 538         /* FLL settings */
 539         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 540         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 541         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 542         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 543         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 544
 545         /* Lock Det settings */
 546         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 547         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 548         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 549         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 550
 551         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 552         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 553         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 554         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 555         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 556         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 557         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 558         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 559         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 560         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 561         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 562         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 563         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 564         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 565         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 566         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 567         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 568         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 569         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 570
 571         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 572         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 573         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 574         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 575         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 576         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 577         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 578         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 579         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 580         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 581         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 582 };
 583
 584 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
 585         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 586         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 587         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 588         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 589         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 590         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 591         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 592         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 593         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 594         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 595         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 596         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 597         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 598         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 599         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 600         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 601         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 602         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 603         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 604         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 605         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 606         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 607         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 608         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 609         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 610         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 611         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 612         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 613         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 614         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 615         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 616         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 617         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 618         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 619         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 620         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 621 };
 622
 623 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
 624         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 625         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 626         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 627         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
 628         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 629 };
 630
 631 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
 632         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
 633         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
 634         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 635         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 636         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 637         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 638         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 639         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 640         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 641         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 642         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 643 };
 644
 645 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
 646         /* FLL settings */
 647         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 648         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 649         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 650         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 651         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 652
 653         /* Lock Det settings */
 654         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 655         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 656         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 657         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 658
 659         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 660         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 661         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 662         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
 663         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
 664         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
 665         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
 666         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 667         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 668         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 669         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 670         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 671         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 672         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 673         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 674         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 675         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 676         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 677         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 678
 679         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 680         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 681         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 682         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 683         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 684         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 685         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 686         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 687         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 688         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 689         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 690
 691         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 692         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 693 };
 694
 695 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
 696         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 697         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 698         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 699         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 700         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 701         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
 702         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 703         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 704         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 705         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 706         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 707         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 708         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
 709         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
 710         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
 711         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
 712         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 713         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 714         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 715         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 716         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 717         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 718         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
 719         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 720         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
 721         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
 722         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
 723         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
 724         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
 725         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
 726         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 727         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 728         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
 729         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
 730         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
 731         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
 732
 733         /* Rate B */
 734         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
 735 };
 736
 737 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
 738         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 739         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
 740         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 741 };
 742
 743 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
 744         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
 745         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
 746         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 747         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 748         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 749         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
 750         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 751         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 752         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 753         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 754         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 755         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
 756         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 757         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
 758         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 759         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 760 };
 761
 762 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
 763         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
 764         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 765         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
 766         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
 767         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
 768         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
 769         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
 770         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
 771 };
 772
 773 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
 774         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 775         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 776         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 777         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
 778         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 779         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 780         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 781         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 782         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 783         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 784         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 785         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 786         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 787         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 788         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 789         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 790         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 791         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 792         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 793         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 794         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 795         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 796         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 797         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 798         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 799         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 800         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 801         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 802         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 803         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
 804         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 805         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 806         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 807         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 808         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 809         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 810         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 811         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 812 };
 813
 814 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
 815         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 816         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 817         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 818         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
 819 };
 820
 821 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
 822         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 823         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 824         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 825         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 826         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
 827         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 828         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
 829         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 830         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 831         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
 832         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
 833         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
 834         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
 835         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
 836         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
 837         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
 838         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 839 };
 840
 841 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
 842         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 843         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 844         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 845         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 846         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 847         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 848         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 849         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 850         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 851         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 852         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 853         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 854         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 855         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 856         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 857         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 858         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 859         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
 860         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 861         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 862         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 863         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 864         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
 865         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 866         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 867         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 868         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 869         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 870         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 871         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 872         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 873         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 874         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 875         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 876         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
 877         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 878         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 879         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 880 };
 881
 882
 883 /* struct qmp_phy_cfg - per-PHY initialization config */
 884 struct qmp_phy_cfg {
 885         /* phy-type - PCIE/UFS/USB */
 886         unsigned int type;
 887         /* number of lanes provided by phy */
 888         int nlanes;
 889
 890         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 891         const struct qmp_phy_init_tbl *serdes_tbl;
 892         int serdes_tbl_num;
 893         const struct qmp_phy_init_tbl *tx_tbl;
 894         int tx_tbl_num;
 895         const struct qmp_phy_init_tbl *rx_tbl;
 896         int rx_tbl_num;
 897         const struct qmp_phy_init_tbl *pcs_tbl;
 898         int pcs_tbl_num;
 899
 900         /* clock ids to be requested */
 901         const char * const *clk_list;
 902         int num_clks;
 903         /* resets to be requested */
 904         const char * const *reset_list;
 905         int num_resets;
 906         /* regulators to be requested */
 907         const char * const *vreg_list;
 908         int num_vregs;
 909
 910         /* array of registers with different offsets */
 911         const unsigned int *regs;
 912
 913         unsigned int start_ctrl;
 914         unsigned int pwrdn_ctrl;
 915         unsigned int mask_com_pcs_ready;
 916
 917         /* true, if PHY has a separate PHY_COM control block */
 918         bool has_phy_com_ctrl;
 919         /* true, if PHY has a reset for individual lanes */
 920         bool has_lane_rst;
 921         /* true, if PHY needs delay after POWER_DOWN */
 922         bool has_pwrdn_delay;
 923         /* power_down delay in usec */
 924         int pwrdn_delay_min;
 925         int pwrdn_delay_max;
 926
 927         /* true, if PHY has a separate DP_COM control block */
 928         bool has_phy_dp_com_ctrl;
 929         /* true, if PHY has secondary tx/rx lanes to be configured */
 930         bool is_dual_lane_phy;
 931
 932         /* true, if PCS block has no separate SW_RESET register */
 933         bool no_pcs_sw_reset;
 934 };
 935
 936 /**
 937  * struct qmp_phy - per-lane phy descriptor
 938  *
 939  * @phy: generic phy
 940  * @tx: iomapped memory space for lane's tx
 941  * @rx: iomapped memory space for lane's rx
 942  * @pcs: iomapped memory space for lane's pcs
 943  * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
 944  * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
 945  * @pcs_misc: iomapped memory space for lane's pcs_misc
 946  * @pipe_clk: pipe lock
 947  * @index: lane index
 948  * @qmp: QMP phy to which this lane belongs
 949  * @lane_rst: lane's reset controller
 950  */
 951 struct qmp_phy {
 952         struct phy *phy;
 953         void __iomem *tx;
 954         void __iomem *rx;
 955         void __iomem *pcs;
 956         void __iomem *tx2;
 957         void __iomem *rx2;
 958         void __iomem *pcs_misc;
 959         struct clk *pipe_clk;
 960         unsigned int index;
 961         struct qcom_qmp *qmp;
 962         struct reset_control *lane_rst;
 963 };
 964
 965 /**
 966  * struct qcom_qmp - structure holding QMP phy block attributes
 967  *
 968  * @dev: device
 969  * @serdes: iomapped memory space for phy's serdes
 970  * @dp_com: iomapped memory space for phy's dp_com control block
 971  *
 972  * @clks: array of clocks required by phy
 973  * @resets: array of resets required by phy
 974  * @vregs: regulator supplies bulk data
 975  *
 976  * @cfg: phy specific configuration
 977  * @phys: array of per-lane phy descriptors
 978  * @phy_mutex: mutex lock for PHY common block initialization
 979  * @init_count: phy common block initialization count
 980  * @phy_initialized: indicate if PHY has been initialized
 981  * @mode: current PHY mode
 982  * @ufs_reset: optional UFS PHY reset handle
 983  */
 984 struct qcom_qmp {
 985         struct device *dev;
 986         void __iomem *serdes;
 987         void __iomem *dp_com;
 988
 989         struct clk_bulk_data *clks;
 990         struct reset_control **resets;
 991         struct regulator_bulk_data *vregs;
 992
 993         const struct qmp_phy_cfg *cfg;
 994         struct qmp_phy **phys;
 995
 996         struct mutex phy_mutex;
 997         int init_count;
 998         bool phy_initialized;
 999         enum phy_mode mode;
1000
1001         struct reset_control *ufs_reset;
1002 };
1003
1004 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1005 {
1006         u32 reg;
1007
1008         reg = readl(base + offset);
1009         reg |= val;
1010         writel(reg, base + offset);
1011
1012         /* ensure that above write is through */
1013         readl(base + offset);
1014 }
1015
1016 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1017 {
1018         u32 reg;
1019
1020         reg = readl(base + offset);
1021         reg &= ~val;
1022         writel(reg, base + offset);
1023
1024         /* ensure that above write is through */
1025         readl(base + offset);
1026 }
1027
1028 /* list of clocks required by phy */
1029 static const char * const msm8996_phy_clk_l[] = {
1030         "aux", "cfg_ahb", "ref",
1031 };
1032
1033 static const char * const qmp_v3_phy_clk_l[] = {
1034         "aux", "cfg_ahb", "ref", "com_aux",
1035 };
1036
1037 static const char * const sdm845_ufs_phy_clk_l[] = {
1038         "ref", "ref_aux",
1039 };
1040
1041 /* list of resets */
1042 static const char * const msm8996_pciephy_reset_l[] = {
1043         "phy", "common", "cfg",
1044 };
1045
1046 static const char * const msm8996_usb3phy_reset_l[] = {
1047         "phy", "common",
1048 };
1049
1050 /* list of regulators */
1051 static const char * const qmp_phy_vreg_l[] = {
1052         "vdda-phy", "vdda-pll",
1053 };
1054
1055 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
1056         .type                   = PHY_TYPE_PCIE,
1057         .nlanes                 = 3,
1058
1059         .serdes_tbl             = msm8996_pcie_serdes_tbl,
1060         .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
1061         .tx_tbl                 = msm8996_pcie_tx_tbl,
1062         .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
1063         .rx_tbl                 = msm8996_pcie_rx_tbl,
1064         .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
1065         .pcs_tbl                = msm8996_pcie_pcs_tbl,
1066         .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
1067         .clk_list               = msm8996_phy_clk_l,
1068         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1069         .reset_list             = msm8996_pciephy_reset_l,
1070         .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
1071         .vreg_list              = qmp_phy_vreg_l,
1072         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1073         .regs                   = pciephy_regs_layout,
1074
1075         .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
1076         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1077         .mask_com_pcs_ready     = PCS_READY,
1078
1079         .has_phy_com_ctrl       = true,
1080         .has_lane_rst           = true,
1081         .has_pwrdn_delay        = true,
1082         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1083         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1084 };
1085
1086 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1087         .type                   = PHY_TYPE_USB3,
1088         .nlanes                 = 1,
1089
1090         .serdes_tbl             = msm8996_usb3_serdes_tbl,
1091         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1092         .tx_tbl                 = msm8996_usb3_tx_tbl,
1093         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1094         .rx_tbl                 = msm8996_usb3_rx_tbl,
1095         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1096         .pcs_tbl                = msm8996_usb3_pcs_tbl,
1097         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1098         .clk_list               = msm8996_phy_clk_l,
1099         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1100         .reset_list             = msm8996_usb3phy_reset_l,
1101         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1102         .vreg_list              = qmp_phy_vreg_l,
1103         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1104         .regs                   = usb3phy_regs_layout,
1105
1106         .start_ctrl             = SERDES_START | PCS_START,
1107         .pwrdn_ctrl             = SW_PWRDN,
1108 };
1109
1110 /* list of resets */
1111 static const char * const ipq8074_pciephy_reset_l[] = {
1112         "phy", "common",
1113 };
1114
1115 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
1116         .type                   = PHY_TYPE_PCIE,
1117         .nlanes                 = 1,
1118
1119         .serdes_tbl             = ipq8074_pcie_serdes_tbl,
1120         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
1121         .tx_tbl                 = ipq8074_pcie_tx_tbl,
1122         .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
1123         .rx_tbl                 = ipq8074_pcie_rx_tbl,
1124         .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
1125         .pcs_tbl                = ipq8074_pcie_pcs_tbl,
1126         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
1127         .clk_list               = NULL,
1128         .num_clks               = 0,
1129         .reset_list             = ipq8074_pciephy_reset_l,
1130         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1131         .vreg_list              = NULL,
1132         .num_vregs              = 0,
1133         .regs                   = pciephy_regs_layout,
1134
1135         .start_ctrl             = SERDES_START | PCS_START,
1136         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1137
1138         .has_phy_com_ctrl       = false,
1139         .has_lane_rst           = false,
1140         .has_pwrdn_delay        = true,
1141         .pwrdn_delay_min        = 995,          /* us */
1142         .pwrdn_delay_max        = 1005,         /* us */
1143 };
1144
1145 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
1146         .type                   = PHY_TYPE_USB3,
1147         .nlanes                 = 1,
1148
1149         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1150         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1151         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1152         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1153         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1154         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1155         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1156         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1157         .clk_list               = qmp_v3_phy_clk_l,
1158         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1159         .reset_list             = msm8996_usb3phy_reset_l,
1160         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1161         .vreg_list              = qmp_phy_vreg_l,
1162         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1163         .regs                   = qmp_v3_usb3phy_regs_layout,
1164
1165         .start_ctrl             = SERDES_START | PCS_START,
1166         .pwrdn_ctrl             = SW_PWRDN,
1167
1168         .has_pwrdn_delay        = true,
1169         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1170         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1171
1172         .has_phy_dp_com_ctrl    = true,
1173         .is_dual_lane_phy       = true,
1174 };
1175
1176 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1177         .type                   = PHY_TYPE_USB3,
1178         .nlanes                 = 1,
1179
1180         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
1181         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1182         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
1183         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1184         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
1185         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1186         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
1187         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1188         .clk_list               = qmp_v3_phy_clk_l,
1189         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1190         .reset_list             = msm8996_usb3phy_reset_l,
1191         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1192         .vreg_list              = qmp_phy_vreg_l,
1193         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1194         .regs                   = qmp_v3_usb3phy_regs_layout,
1195
1196         .start_ctrl             = SERDES_START | PCS_START,
1197         .pwrdn_ctrl             = SW_PWRDN,
1198
1199         .has_pwrdn_delay        = true,
1200         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1201         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1202 };
1203
1204 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1205         .type                   = PHY_TYPE_UFS,
1206         .nlanes                 = 2,
1207
1208         .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
1209         .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
1210         .tx_tbl                 = sdm845_ufsphy_tx_tbl,
1211         .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
1212         .rx_tbl                 = sdm845_ufsphy_rx_tbl,
1213         .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
1214         .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
1215         .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
1216         .clk_list               = sdm845_ufs_phy_clk_l,
1217         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1218         .vreg_list              = qmp_phy_vreg_l,
1219         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1220         .regs                   = sdm845_ufsphy_regs_layout,
1221
1222         .start_ctrl             = SERDES_START,
1223         .pwrdn_ctrl             = SW_PWRDN,
1224
1225         .is_dual_lane_phy       = true,
1226         .no_pcs_sw_reset        = true,
1227 };
1228
1229 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
1230         .type                   = PHY_TYPE_PCIE,
1231         .nlanes                 = 1,
1232
1233         .serdes_tbl             = msm8998_pcie_serdes_tbl,
1234         .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
1235         .tx_tbl                 = msm8998_pcie_tx_tbl,
1236         .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
1237         .rx_tbl                 = msm8998_pcie_rx_tbl,
1238         .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
1239         .pcs_tbl                = msm8998_pcie_pcs_tbl,
1240         .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
1241         .clk_list               = msm8996_phy_clk_l,
1242         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1243         .reset_list             = ipq8074_pciephy_reset_l,
1244         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1245         .vreg_list              = qmp_phy_vreg_l,
1246         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1247         .regs                   = pciephy_regs_layout,
1248
1249         .start_ctrl             = SERDES_START | PCS_START,
1250         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1251 };
1252
1253 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1254         .type                   = PHY_TYPE_USB3,
1255         .nlanes                 = 1,
1256
1257         .serdes_tbl             = msm8998_usb3_serdes_tbl,
1258         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1259         .tx_tbl                 = msm8998_usb3_tx_tbl,
1260         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1261         .rx_tbl                 = msm8998_usb3_rx_tbl,
1262         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1263         .pcs_tbl                = msm8998_usb3_pcs_tbl,
1264         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1265         .clk_list               = msm8996_phy_clk_l,
1266         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1267         .reset_list             = msm8996_usb3phy_reset_l,
1268         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1269         .vreg_list              = qmp_phy_vreg_l,
1270         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1271         .regs                   = qmp_v3_usb3phy_regs_layout,
1272
1273         .start_ctrl             = SERDES_START | PCS_START,
1274         .pwrdn_ctrl             = SW_PWRDN,
1275
1276         .is_dual_lane_phy       = true,
1277 };
1278
1279 static void qcom_qmp_phy_configure(void __iomem *base,
1280                                    const unsigned int *regs,
1281                                    const struct qmp_phy_init_tbl tbl[],
1282                                    int num)
1283 {
1284         int i;
1285         const struct qmp_phy_init_tbl *t = tbl;
1286
1287         if (!t)
1288                 return;
1289
1290         for (i = 0; i < num; i++, t++) {
1291                 if (t->in_layout)
1292                         writel(t->val, base + regs[t->offset]);
1293                 else
1294                         writel(t->val, base + t->offset);
1295         }
1296 }
1297
1298 static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
1299 {
1300         struct qcom_qmp *qmp = qphy->qmp;
1301         const struct qmp_phy_cfg *cfg = qmp->cfg;
1302         void __iomem *serdes = qmp->serdes;
1303         void __iomem *pcs = qphy->pcs;
1304         void __iomem *dp_com = qmp->dp_com;
1305         int ret, i;
1306
1307         mutex_lock(&qmp->phy_mutex);
1308         if (qmp->init_count++) {
1309                 mutex_unlock(&qmp->phy_mutex);
1310                 return 0;
1311         }
1312
1313         /* turn on regulator supplies */
1314         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1315         if (ret) {
1316                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1317                 goto err_reg_enable;
1318         }
1319
1320         for (i = 0; i < cfg->num_resets; i++) {
1321                 ret = reset_control_assert(qmp->resets[i]);
1322                 if (ret) {
1323                         dev_err(qmp->dev, "%s reset assert failed\n",
1324                                 cfg->reset_list[i]);
1325                         goto err_rst_assert;
1326                 }
1327         }
1328
1329         for (i = cfg->num_resets - 1; i >= 0; i--) {
1330                 ret = reset_control_deassert(qmp->resets[i]);
1331                 if (ret) {
1332                         dev_err(qmp->dev, "%s reset deassert failed\n",
1333                                 qmp->cfg->reset_list[i]);
1334                         goto err_rst;
1335                 }
1336         }
1337
1338         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1339         if (ret) {
1340                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1341                 goto err_rst;
1342         }
1343
1344         if (cfg->has_phy_dp_com_ctrl) {
1345                 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
1346                              SW_PWRDN);
1347                 /* override hardware control for reset of qmp phy */
1348                 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1349                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1350                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1351
1352                 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
1353                              USB3_MODE | DP_MODE);
1354
1355                 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
1356                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1357                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1358                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1359         }
1360
1361         if (cfg->has_phy_com_ctrl)
1362                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1363                              SW_PWRDN);
1364         else
1365                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1366
1367         /* Serdes configuration */
1368         qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
1369                                cfg->serdes_tbl_num);
1370
1371         if (cfg->has_phy_com_ctrl) {
1372                 void __iomem *status;
1373                 unsigned int mask, val;
1374
1375                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
1376                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1377                              SERDES_START | PCS_START);
1378
1379                 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
1380                 mask = cfg->mask_com_pcs_ready;
1381
1382                 ret = readl_poll_timeout(status, val, (val & mask), 10,
1383                                          PHY_INIT_COMPLETE_TIMEOUT);
1384                 if (ret) {
1385                         dev_err(qmp->dev,
1386                                 "phy common block init timed-out\n");
1387                         goto err_com_init;
1388                 }
1389         }
1390
1391         mutex_unlock(&qmp->phy_mutex);
1392
1393         return 0;
1394
1395 err_com_init:
1396         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1397 err_rst:
1398         while (++i < cfg->num_resets)
1399                 reset_control_assert(qmp->resets[i]);
1400 err_rst_assert:
1401         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1402 err_reg_enable:
1403         mutex_unlock(&qmp->phy_mutex);
1404
1405         return ret;
1406 }
1407
1408 static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
1409 {
1410         const struct qmp_phy_cfg *cfg = qmp->cfg;
1411         void __iomem *serdes = qmp->serdes;
1412         int i = cfg->num_resets;
1413
1414         mutex_lock(&qmp->phy_mutex);
1415         if (--qmp->init_count) {
1416                 mutex_unlock(&qmp->phy_mutex);
1417                 return 0;
1418         }
1419
1420         reset_control_assert(qmp->ufs_reset);
1421         if (cfg->has_phy_com_ctrl) {
1422                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1423                              SERDES_START | PCS_START);
1424                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
1425                              SW_RESET);
1426                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1427                              SW_PWRDN);
1428         }
1429
1430         while (--i >= 0)
1431                 reset_control_assert(qmp->resets[i]);
1432
1433         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1434
1435         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1436
1437         mutex_unlock(&qmp->phy_mutex);
1438
1439         return 0;
1440 }
1441
1442 static int qcom_qmp_phy_enable(struct phy *phy)
1443 {
1444         struct qmp_phy *qphy = phy_get_drvdata(phy);
1445         struct qcom_qmp *qmp = qphy->qmp;
1446         const struct qmp_phy_cfg *cfg = qmp->cfg;
1447         void __iomem *tx = qphy->tx;
1448         void __iomem *rx = qphy->rx;
1449         void __iomem *pcs = qphy->pcs;
1450         void __iomem *dp_com = qmp->dp_com;
1451         void __iomem *status;
1452         unsigned int mask, val, ready;
1453         int ret;
1454
1455         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1456
1457         if (cfg->no_pcs_sw_reset) {
1458                 /*
1459                  * Get UFS reset, which is delayed until now to avoid a
1460                  * circular dependency where UFS needs its PHY, but the PHY
1461                  * needs this UFS reset.
1462                  */
1463                 if (!qmp->ufs_reset) {
1464                         qmp->ufs_reset =
1465                                 devm_reset_control_get_exclusive(qmp->dev,
1466                                                                  "ufsphy");
1467
1468                         if (IS_ERR(qmp->ufs_reset)) {
1469                                 ret = PTR_ERR(qmp->ufs_reset);
1470                                 dev_err(qmp->dev,
1471                                         "failed to get UFS reset: %d\n",
1472                                         ret);
1473
1474                                 qmp->ufs_reset = NULL;
1475                                 return ret;
1476                         }
1477                 }
1478
1479                 ret = reset_control_assert(qmp->ufs_reset);
1480                 if (ret)
1481                         goto err_lane_rst;
1482         }
1483
1484         ret = qcom_qmp_phy_com_init(qphy);
1485         if (ret)
1486                 return ret;
1487
1488         if (cfg->has_lane_rst) {
1489                 ret = reset_control_deassert(qphy->lane_rst);
1490                 if (ret) {
1491                         dev_err(qmp->dev, "lane%d reset deassert failed\n",
1492                                 qphy->index);
1493                         goto err_lane_rst;
1494                 }
1495         }
1496
1497         ret = clk_prepare_enable(qphy->pipe_clk);
1498         if (ret) {
1499                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1500                 goto err_clk_enable;
1501         }
1502
1503         /* Tx, Rx, and PCS configurations */
1504         qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
1505         /* Configuration for other LANE for USB-DP combo PHY */
1506         if (cfg->is_dual_lane_phy)
1507                 qcom_qmp_phy_configure(qphy->tx2, cfg->regs,
1508                                        cfg->tx_tbl, cfg->tx_tbl_num);
1509
1510         qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
1511         if (cfg->is_dual_lane_phy)
1512                 qcom_qmp_phy_configure(qphy->rx2, cfg->regs,
1513                                        cfg->rx_tbl, cfg->rx_tbl_num);
1514
1515         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1516         ret = reset_control_deassert(qmp->ufs_reset);
1517         if (ret)
1518                 goto err_lane_rst;
1519
1520         /*
1521          * Pull out PHY from POWER DOWN state.
1522          * This is active low enable signal to power-down PHY.
1523          */
1524         if(cfg->type == PHY_TYPE_PCIE)
1525                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1526
1527         if (cfg->has_pwrdn_delay)
1528                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
1529
1530         /* Pull PHY out of reset state */
1531         if (!cfg->no_pcs_sw_reset)
1532                 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1533
1534         if (cfg->has_phy_dp_com_ctrl)
1535                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
1536
1537         /* start SerDes and Phy-Coding-Sublayer */
1538         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1539
1540         if (cfg->type == PHY_TYPE_UFS) {
1541                 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1542                 mask = PCS_READY;
1543                 ready = PCS_READY;
1544         } else {
1545                 status = pcs + cfg->regs[QPHY_PCS_STATUS];
1546                 mask = PHYSTATUS;
1547                 ready = 0;
1548         }
1549
1550         ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
1551                                  PHY_INIT_COMPLETE_TIMEOUT);
1552         if (ret) {
1553                 dev_err(qmp->dev, "phy initialization timed-out\n");
1554                 goto err_pcs_ready;
1555         }
1556         qmp->phy_initialized = true;
1557         return 0;
1558
1559 err_pcs_ready:
1560         reset_control_assert(qmp->ufs_reset);
1561         clk_disable_unprepare(qphy->pipe_clk);
1562 err_clk_enable:
1563         if (cfg->has_lane_rst)
1564                 reset_control_assert(qphy->lane_rst);
1565 err_lane_rst:
1566         qcom_qmp_phy_com_exit(qmp);
1567
1568         return ret;
1569 }
1570
1571 static int qcom_qmp_phy_disable(struct phy *phy)
1572 {
1573         struct qmp_phy *qphy = phy_get_drvdata(phy);
1574         struct qcom_qmp *qmp = qphy->qmp;
1575         const struct qmp_phy_cfg *cfg = qmp->cfg;
1576
1577         clk_disable_unprepare(qphy->pipe_clk);
1578
1579         /* PHY reset */
1580         if (!cfg->no_pcs_sw_reset)
1581                 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1582
1583         /* stop SerDes and Phy-Coding-Sublayer */
1584         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1585
1586         /* Put PHY into POWER DOWN state: active low */
1587         qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1588
1589         if (cfg->has_lane_rst)
1590                 reset_control_assert(qphy->lane_rst);
1591
1592         qcom_qmp_phy_com_exit(qmp);
1593
1594         qmp->phy_initialized = false;
1595
1596         return 0;
1597 }
1598
1599 static int qcom_qmp_phy_set_mode(struct phy *phy,
1600                                  enum phy_mode mode, int submode)
1601 {
1602         struct qmp_phy *qphy = phy_get_drvdata(phy);
1603         struct qcom_qmp *qmp = qphy->qmp;
1604
1605         qmp->mode = mode;
1606
1607         return 0;
1608 }
1609
1610 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
1611 {
1612         struct qcom_qmp *qmp = qphy->qmp;
1613         const struct qmp_phy_cfg *cfg = qmp->cfg;
1614         void __iomem *pcs = qphy->pcs;
1615         void __iomem *pcs_misc = qphy->pcs_misc;
1616         u32 intr_mask;
1617
1618         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1619             qmp->mode == PHY_MODE_USB_DEVICE_SS)
1620                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1621         else
1622                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1623
1624         /* Clear any pending interrupts status */
1625         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1626         /* Writing 1 followed by 0 clears the interrupt */
1627         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1628
1629         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1630                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1631
1632         /* Enable required PHY autonomous mode interrupts */
1633         qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1634
1635         /* Enable i/o clamp_n for autonomous mode */
1636         if (pcs_misc)
1637                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1638 }
1639
1640 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
1641 {
1642         struct qcom_qmp *qmp = qphy->qmp;
1643         const struct qmp_phy_cfg *cfg = qmp->cfg;
1644         void __iomem *pcs = qphy->pcs;
1645         void __iomem *pcs_misc = qphy->pcs_misc;
1646
1647         /* Disable i/o clamp_n on resume for normal mode */
1648         if (pcs_misc)
1649                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1650
1651         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1652                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1653
1654         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1655         /* Writing 1 followed by 0 clears the interrupt */
1656         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1657 }
1658
1659 static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
1660 {
1661         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1662         struct qmp_phy *qphy = qmp->phys[0];
1663         const struct qmp_phy_cfg *cfg = qmp->cfg;
1664
1665         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1666
1667         /* Supported only for USB3 PHY */
1668         if (cfg->type != PHY_TYPE_USB3)
1669                 return 0;
1670
1671         if (!qmp->phy_initialized) {
1672                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1673                 return 0;
1674         }
1675
1676         qcom_qmp_phy_enable_autonomous_mode(qphy);
1677
1678         clk_disable_unprepare(qphy->pipe_clk);
1679         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1680
1681         return 0;
1682 }
1683
1684 static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
1685 {
1686         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1687         struct qmp_phy *qphy = qmp->phys[0];
1688         const struct qmp_phy_cfg *cfg = qmp->cfg;
1689         int ret = 0;
1690
1691         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1692
1693         /* Supported only for USB3 PHY */
1694         if (cfg->type != PHY_TYPE_USB3)
1695                 return 0;
1696
1697         if (!qmp->phy_initialized) {
1698                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1699                 return 0;
1700         }
1701
1702         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1703         if (ret) {
1704                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1705                 return ret;
1706         }
1707
1708         ret = clk_prepare_enable(qphy->pipe_clk);
1709         if (ret) {
1710                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1711                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1712                 return ret;
1713         }
1714
1715         qcom_qmp_phy_disable_autonomous_mode(qphy);
1716
1717         return 0;
1718 }
1719
1720 static int qcom_qmp_phy_vreg_init(struct device *dev)
1721 {
1722         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1723         int num = qmp->cfg->num_vregs;
1724         int i;
1725
1726         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1727         if (!qmp->vregs)
1728                 return -ENOMEM;
1729
1730         for (i = 0; i < num; i++)
1731                 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
1732
1733         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1734 }
1735
1736 static int qcom_qmp_phy_reset_init(struct device *dev)
1737 {
1738         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1739         int i;
1740
1741         qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
1742                                    sizeof(*qmp->resets), GFP_KERNEL);
1743         if (!qmp->resets)
1744                 return -ENOMEM;
1745
1746         for (i = 0; i < qmp->cfg->num_resets; i++) {
1747                 struct reset_control *rst;
1748                 const char *name = qmp->cfg->reset_list[i];
1749
1750                 rst = devm_reset_control_get(dev, name);
1751                 if (IS_ERR(rst)) {
1752                         dev_err(dev, "failed to get %s reset\n", name);
1753                         return PTR_ERR(rst);
1754                 }
1755                 qmp->resets[i] = rst;
1756         }
1757
1758         return 0;
1759 }
1760
1761 static int qcom_qmp_phy_clk_init(struct device *dev)
1762 {
1763         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1764         int num = qmp->cfg->num_clks;
1765         int i;
1766
1767         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1768         if (!qmp->clks)
1769                 return -ENOMEM;
1770
1771         for (i = 0; i < num; i++)
1772                 qmp->clks[i].id = qmp->cfg->clk_list[i];
1773
1774         return devm_clk_bulk_get(dev, num, qmp->clks);
1775 }
1776
1777 static void phy_pipe_clk_release_provider(void *res)
1778 {
1779         of_clk_del_provider(res);
1780 }
1781
1782 /*
1783  * Register a fixed rate pipe clock.
1784  *
1785  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1786  * controls it. The <s>_pipe_clk coming out of the GCC is requested
1787  * by the PHY driver for its operations.
1788  * We register the <s>_pipe_clksrc here. The gcc driver takes care
1789  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1790  * Below picture shows this relationship.
1791  *
1792  *         +---------------+
1793  *         |   PHY block   |<<---------------------------------------+
1794  *         |               |                                         |
1795  *         |   +-------+   |                   +-----+               |
1796  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1797  *    clk  |   +-------+   |                   +-----+
1798  *         +---------------+
1799  */
1800 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
1801 {
1802         struct clk_fixed_rate *fixed;
1803         struct clk_init_data init = { };
1804         int ret;
1805
1806         if ((qmp->cfg->type != PHY_TYPE_USB3) &&
1807             (qmp->cfg->type != PHY_TYPE_PCIE)) {
1808                 /* not all phys register pipe clocks, so return success */
1809                 return 0;
1810         }
1811
1812         ret = of_property_read_string(np, "clock-output-names", &init.name);
1813         if (ret) {
1814                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
1815                 return ret;
1816         }
1817
1818         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
1819         if (!fixed)
1820                 return -ENOMEM;
1821
1822         init.ops = &clk_fixed_rate_ops;
1823
1824         /* controllers using QMP phys use 125MHz pipe clock interface */
1825         fixed->fixed_rate = 125000000;
1826         fixed->hw.init = &init;
1827
1828         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
1829         if (ret)
1830                 return ret;
1831
1832         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
1833         if (ret)
1834                 return ret;
1835
1836         /*
1837          * Roll a devm action because the clock provider is the child node, but
1838          * the child node is not actually a device.
1839          */
1840         ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np);
1841         if (ret)
1842                 phy_pipe_clk_release_provider(np);
1843
1844         return ret;
1845 }
1846
1847 static const struct phy_ops qcom_qmp_phy_gen_ops = {
1848         .init           = qcom_qmp_phy_enable,
1849         .exit           = qcom_qmp_phy_disable,
1850         .set_mode       = qcom_qmp_phy_set_mode,
1851         .owner          = THIS_MODULE,
1852 };
1853
1854 static const struct phy_ops qcom_qmp_ufs_ops = {
1855         .power_on       = qcom_qmp_phy_enable,
1856         .power_off      = qcom_qmp_phy_disable,
1857         .set_mode       = qcom_qmp_phy_set_mode,
1858         .owner          = THIS_MODULE,
1859 };
1860
1861 static
1862 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
1863 {
1864         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1865         struct phy *generic_phy;
1866         struct qmp_phy *qphy;
1867         const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
1868         char prop_name[MAX_PROP_NAME];
1869         int ret;
1870
1871         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
1872         if (!qphy)
1873                 return -ENOMEM;
1874
1875         /*
1876          * Get memory resources for each phy lane:
1877          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1878          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
1879          * For single lane PHYs: pcs_misc (optional) -> 3.
1880          */
1881         qphy->tx = of_iomap(np, 0);
1882         if (!qphy->tx)
1883                 return -ENOMEM;
1884
1885         qphy->rx = of_iomap(np, 1);
1886         if (!qphy->rx)
1887                 return -ENOMEM;
1888
1889         qphy->pcs = of_iomap(np, 2);
1890         if (!qphy->pcs)
1891                 return -ENOMEM;
1892
1893         /*
1894          * If this is a dual-lane PHY, then there should be registers for the
1895          * second lane. Some old device trees did not specify this, so fall
1896          * back to old legacy behavior of assuming they can be reached at an
1897          * offset from the first lane.
1898          */
1899         if (qmp->cfg->is_dual_lane_phy) {
1900                 qphy->tx2 = of_iomap(np, 3);
1901                 qphy->rx2 = of_iomap(np, 4);
1902                 if (!qphy->tx2 || !qphy->rx2) {
1903                         dev_warn(dev,
1904                                  "Underspecified device tree, falling back to legacy register regions\n");
1905
1906                         /* In the old version, pcs_misc is at index 3. */
1907                         qphy->pcs_misc = qphy->tx2;
1908                         qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
1909                         qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
1910
1911                 } else {
1912                         qphy->pcs_misc = of_iomap(np, 5);
1913                 }
1914
1915         } else {
1916                 qphy->pcs_misc = of_iomap(np, 3);
1917         }
1918
1919         if (!qphy->pcs_misc)
1920                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1921
1922         /*
1923          * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
1924          * based phys, so they essentially have pipe clock. So,
1925          * we return error in case phy is USB3 or PIPE type.
1926          * Otherwise, we initialize pipe clock to NULL for
1927          * all phys that don't need this.
1928          */
1929         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
1930         qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
1931         if (IS_ERR(qphy->pipe_clk)) {
1932                 if (qmp->cfg->type == PHY_TYPE_PCIE ||
1933                     qmp->cfg->type == PHY_TYPE_USB3) {
1934                         ret = PTR_ERR(qphy->pipe_clk);
1935                         if (ret != -EPROBE_DEFER)
1936                                 dev_err(dev,
1937                                         "failed to get lane%d pipe_clk, %d\n",
1938                                         id, ret);
1939                         return ret;
1940                 }
1941                 qphy->pipe_clk = NULL;
1942         }
1943
1944         /* Get lane reset, if any */
1945         if (qmp->cfg->has_lane_rst) {
1946                 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
1947                 qphy->lane_rst = of_reset_control_get(np, prop_name);
1948                 if (IS_ERR(qphy->lane_rst)) {
1949                         dev_err(dev, "failed to get lane%d reset\n", id);
1950                         return PTR_ERR(qphy->lane_rst);
1951                 }
1952         }
1953
1954         if (qmp->cfg->type == PHY_TYPE_UFS)
1955                 ops = &qcom_qmp_ufs_ops;
1956
1957         generic_phy = devm_phy_create(dev, np, ops);
1958         if (IS_ERR(generic_phy)) {
1959                 ret = PTR_ERR(generic_phy);
1960                 dev_err(dev, "failed to create qphy %d\n", ret);
1961                 return ret;
1962         }
1963
1964         qphy->phy = generic_phy;
1965         qphy->index = id;
1966         qphy->qmp = qmp;
1967         qmp->phys[id] = qphy;
1968         phy_set_drvdata(generic_phy, qphy);
1969
1970         return 0;
1971 }
1972
1973 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
1974         {
1975                 .compatible = "qcom,msm8996-qmp-pcie-phy",
1976                 .data = &msm8996_pciephy_cfg,
1977         }, {
1978                 .compatible = "qcom,msm8996-qmp-usb3-phy",
1979                 .data = &msm8996_usb3phy_cfg,
1980         }, {
1981                 .compatible = "qcom,msm8998-qmp-pcie-phy",
1982                 .data = &msm8998_pciephy_cfg,
1983         }, {
1984                 .compatible = "qcom,msm8998-qmp-ufs-phy",
1985                 .data = &sdm845_ufsphy_cfg,
1986         }, {
1987                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
1988                 .data = &ipq8074_pciephy_cfg,
1989         }, {
1990                 .compatible = "qcom,sdm845-qmp-usb3-phy",
1991                 .data = &qmp_v3_usb3phy_cfg,
1992         }, {
1993                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
1994                 .data = &qmp_v3_usb3_uniphy_cfg,
1995         }, {
1996                 .compatible = "qcom,sdm845-qmp-ufs-phy",
1997                 .data = &sdm845_ufsphy_cfg,
1998         }, {
1999                 .compatible = "qcom,msm8998-qmp-usb3-phy",
2000                 .data = &msm8998_usb3phy_cfg,
2001         },
2002         { },
2003 };
2004 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
2005
2006 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
2007         SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
2008                            qcom_qmp_phy_runtime_resume, NULL)
2009 };
2010
2011 static int qcom_qmp_phy_probe(struct platform_device *pdev)
2012 {
2013         struct qcom_qmp *qmp;
2014         struct device *dev = &pdev->dev;
2015         struct resource *res;
2016         struct device_node *child;
2017         struct phy_provider *phy_provider;
2018         void __iomem *base;
2019         int num, id;
2020         int ret;
2021
2022         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2023         if (!qmp)
2024                 return -ENOMEM;
2025
2026         qmp->dev = dev;
2027         dev_set_drvdata(dev, qmp);
2028
2029         /* Get the specific init parameters of QMP phy */
2030         qmp->cfg = of_device_get_match_data(dev);
2031         if (!qmp->cfg)
2032                 return -EINVAL;
2033
2034         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2035         base = devm_ioremap_resource(dev, res);
2036         if (IS_ERR(base))
2037                 return PTR_ERR(base);
2038
2039         /* per PHY serdes; usually located at base address */
2040         qmp->serdes = base;
2041
2042         /* per PHY dp_com; if PHY has dp_com control block */
2043         if (qmp->cfg->has_phy_dp_com_ctrl) {
2044                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2045                                                    "dp_com");
2046                 base = devm_ioremap_resource(dev, res);
2047                 if (IS_ERR(base))
2048                         return PTR_ERR(base);
2049
2050                 qmp->dp_com = base;
2051         }
2052
2053         mutex_init(&qmp->phy_mutex);
2054
2055         ret = qcom_qmp_phy_clk_init(dev);
2056         if (ret)
2057                 return ret;
2058
2059         ret = qcom_qmp_phy_reset_init(dev);
2060         if (ret)
2061                 return ret;
2062
2063         ret = qcom_qmp_phy_vreg_init(dev);
2064         if (ret) {
2065                 if (ret != -EPROBE_DEFER)
2066                         dev_err(dev, "failed to get regulator supplies: %d\n",
2067                                 ret);
2068                 return ret;
2069         }
2070
2071         num = of_get_available_child_count(dev->of_node);
2072         /* do we have a rogue child node ? */
2073         if (num > qmp->cfg->nlanes)
2074                 return -EINVAL;
2075
2076         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
2077         if (!qmp->phys)
2078                 return -ENOMEM;
2079
2080         id = 0;
2081         pm_runtime_set_active(dev);
2082         pm_runtime_enable(dev);
2083         /*
2084          * Prevent runtime pm from being ON by default. Users can enable
2085          * it using power/control in sysfs.
2086          */
2087         pm_runtime_forbid(dev);
2088
2089         for_each_available_child_of_node(dev->of_node, child) {
2090                 /* Create per-lane phy */
2091                 ret = qcom_qmp_phy_create(dev, child, id);
2092                 if (ret) {
2093                         dev_err(dev, "failed to create lane%d phy, %d\n",
2094                                 id, ret);
2095                         pm_runtime_disable(dev);
2096                         return ret;
2097                 }
2098
2099                 /*
2100                  * Register the pipe clock provided by phy.
2101                  * See function description to see details of this pipe clock.
2102                  */
2103                 ret = phy_pipe_clk_register(qmp, child);
2104                 if (ret) {
2105                         dev_err(qmp->dev,
2106                                 "failed to register pipe clock source\n");
2107                         pm_runtime_disable(dev);
2108                         return ret;
2109                 }
2110                 id++;
2111         }
2112
2113         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2114         if (!IS_ERR(phy_provider))
2115                 dev_info(dev, "Registered Qcom-QMP phy\n");
2116         else
2117                 pm_runtime_disable(dev);
2118
2119         return PTR_ERR_OR_ZERO(phy_provider);
2120 }
2121
2122 static struct platform_driver qcom_qmp_phy_driver = {
2123         .probe          = qcom_qmp_phy_probe,
2124         .driver = {
2125                 .name   = "qcom-qmp-phy",
2126                 .pm     = &qcom_qmp_phy_pm_ops,
2127                 .of_match_table = qcom_qmp_phy_of_match_table,
2128         },
2129 };
2130
2131 module_platform_driver(qcom_qmp_phy_driver);
2132
2133 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2134 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
2135 MODULE_LICENSE("GPL v2");