drivers/phy/phy-stm32-usbphyc.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <generic-phy.h>
  12 #include <reset.h>
  13 #include <syscon.h>
  14 #include <usb.h>
  15 #include <asm/io.h>
  16 #include <linux/bitops.h>
  17 #include <power/regulator.h>
  18
  19 /* USBPHYC registers */
  20 #define STM32_USBPHYC_PLL       0x0
  21 #define STM32_USBPHYC_MISC      0x8
  22
  23 /* STM32_USBPHYC_PLL bit fields */
  24 #define PLLNDIV                 GENMASK(6, 0)
  25 #define PLLNDIV_SHIFT           0
  26 #define PLLFRACIN               GENMASK(25, 10)
  27 #define PLLFRACIN_SHIFT         10
  28 #define PLLEN                   BIT(26)
  29 #define PLLSTRB                 BIT(27)
  30 #define PLLSTRBYP               BIT(28)
  31 #define PLLFRACCTL              BIT(29)
  32 #define PLLDITHEN0              BIT(30)
  33 #define PLLDITHEN1              BIT(31)
  34
  35 /* STM32_USBPHYC_MISC bit fields */
  36 #define SWITHOST                BIT(0)
  37
  38 #define MAX_PHYS                2
  39
  40 /* max 100 us for PLL lock and 100 us for PHY init */
  41 #define PLL_INIT_TIME_US        200
  42 #define PLL_PWR_DOWN_TIME_US    5
  43 #define PLL_FVCO                2880     /* in MHz */
  44 #define PLL_INFF_MIN_RATE       19200000 /* in Hz */
  45 #define PLL_INFF_MAX_RATE       38400000 /* in Hz */
  46
  47 struct pll_params {
  48         u8 ndiv;
  49         u16 frac;
  50 };
  51
  52 struct stm32_usbphyc {
  53         fdt_addr_t base;
  54         struct clk clk;
  55         struct udevice *vdda1v1;
  56         struct udevice *vdda1v8;
  57         struct stm32_usbphyc_phy {
  58                 struct udevice *vdd;
  59                 bool init;
  60                 bool powered;
  61         } phys[MAX_PHYS];
  62 };
  63
  64 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
  65                                          struct pll_params *pll_params)
  66 {
  67         unsigned long long fvco, ndiv, frac;
  68
  69         /*
  70          *    | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
  71          *    | FVCO = 2880MHz
  72          *    | NDIV = integer part of input bits to set the LDF
  73          *    | FRACT = fractional part of input bits to set the LDF
  74          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
  75          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
  76          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
  77          */
  78         fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
  79
  80         ndiv = fvco;
  81         do_div(ndiv, (clk_rate * 2));
  82         pll_params->ndiv = (u8)ndiv;
  83
  84         frac = fvco * (1 << 16);
  85         do_div(frac, (clk_rate * 2));
  86         frac = frac - (ndiv * (1 << 16));
  87         pll_params->frac = (u16)frac;
  88 }
  89
  90 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
  91 {
  92         struct pll_params pll_params;
  93         u32 clk_rate = clk_get_rate(&usbphyc->clk);
  94         u32 usbphyc_pll;
  95
  96         if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
  97                 pr_debug("%s: input clk freq (%dHz) out of range\n",
  98                          __func__, clk_rate);
  99                 return -EINVAL;
 100         }
 101
 102         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 103
 104         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
 105         usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
 106
 107         if (pll_params.frac) {
 108                 usbphyc_pll |= PLLFRACCTL;
 109                 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
 110                                  & PLLFRACIN);
 111         }
 112
 113         writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 114
 115         pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
 116                  clk_rate, pll_params.ndiv, pll_params.frac);
 117
 118         return 0;
 119 }
 120
 121 static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
 122 {
 123         int i;
 124
 125         for (i = 0; i < MAX_PHYS; i++) {
 126                 if (usbphyc->phys[i].init)
 127                         return true;
 128         }
 129
 130         return false;
 131 }
 132
 133 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
 134 {
 135         int i;
 136
 137         for (i = 0; i < MAX_PHYS; i++) {
 138                 if (usbphyc->phys[i].powered)
 139                         return true;
 140         }
 141
 142         return false;
 143 }
 144
 145 static int stm32_usbphyc_phy_init(struct phy *phy)
 146 {
 147         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 148         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 149         bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
 150                      true : false;
 151         int ret;
 152
 153         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 154         /* Check if one phy port has already configured the pll */
 155         if (pllen && stm32_usbphyc_is_init(usbphyc))
 156                 goto initialized;
 157
 158         if (usbphyc->vdda1v1) {
 159                 ret = regulator_set_enable(usbphyc->vdda1v1, true);
 160                 if (ret)
 161                         return ret;
 162         }
 163
 164         if (usbphyc->vdda1v8) {
 165                 ret = regulator_set_enable(usbphyc->vdda1v8, true);
 166                 if (ret)
 167                         return ret;
 168         }
 169
 170         if (pllen) {
 171                 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 172                 udelay(PLL_PWR_DOWN_TIME_US);
 173         }
 174
 175         ret = stm32_usbphyc_pll_init(usbphyc);
 176         if (ret)
 177                 return ret;
 178
 179         setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 180
 181         /* We must wait PLL_INIT_TIME_US before using PHY */
 182         udelay(PLL_INIT_TIME_US);
 183
 184         if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
 185                 return -EIO;
 186
 187 initialized:
 188         usbphyc_phy->init = true;
 189
 190         return 0;
 191 }
 192
 193 static int stm32_usbphyc_phy_exit(struct phy *phy)
 194 {
 195         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 196         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 197         int ret;
 198
 199         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 200         usbphyc_phy->init = false;
 201
 202         /* Check if other phy port requires pllen */
 203         if (stm32_usbphyc_is_init(usbphyc))
 204                 return 0;
 205
 206         clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 207
 208         /*
 209          * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
 210          * bit is still clear
 211          */
 212         udelay(PLL_PWR_DOWN_TIME_US);
 213
 214         if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
 215                 return -EIO;
 216
 217         if (usbphyc->vdda1v1) {
 218                 ret = regulator_set_enable(usbphyc->vdda1v1, false);
 219                 if (ret)
 220                         return ret;
 221         }
 222
 223         if (usbphyc->vdda1v8) {
 224                 ret = regulator_set_enable(usbphyc->vdda1v8, false);
 225                 if (ret)
 226                         return ret;
 227         }
 228
 229         return 0;
 230 }
 231
 232 static int stm32_usbphyc_phy_power_on(struct phy *phy)
 233 {
 234         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 235         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 236         int ret;
 237
 238         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 239         if (usbphyc_phy->vdd) {
 240                 ret = regulator_set_enable(usbphyc_phy->vdd, true);
 241                 if (ret)
 242                         return ret;
 243         }
 244
 245         usbphyc_phy->powered = true;
 246
 247         return 0;
 248 }
 249
 250 static int stm32_usbphyc_phy_power_off(struct phy *phy)
 251 {
 252         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 253         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 254         int ret;
 255
 256         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 257         usbphyc_phy->powered = false;
 258
 259         if (stm32_usbphyc_is_powered(usbphyc))
 260                 return 0;
 261
 262         if (usbphyc_phy->vdd) {
 263                 ret = regulator_set_enable(usbphyc_phy->vdd, false);
 264                 if (ret)
 265                         return ret;
 266         }
 267
 268         return 0;
 269 }
 270
 271 static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
 272                                        char *supply_name,
 273                                        struct udevice **regulator)
 274 {
 275         struct ofnode_phandle_args regulator_phandle;
 276         int ret;
 277
 278         ret = ofnode_parse_phandle_with_args(node, supply_name,
 279                                              NULL, 0, 0,
 280                                              &regulator_phandle);
 281         if (ret) {
 282                 dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
 283                 return ret;
 284         }
 285
 286         ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
 287                                           regulator_phandle.node,
 288                                           regulator);
 289
 290         if (ret) {
 291                 dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
 292                 return ret;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int stm32_usbphyc_of_xlate(struct phy *phy,
 299                                   struct ofnode_phandle_args *args)
 300 {
 301         if (args->args_count < 1)
 302                 return -ENODEV;
 303
 304         if (args->args[0] >= MAX_PHYS)
 305                 return -ENODEV;
 306
 307         phy->id = args->args[0];
 308
 309         if ((phy->id == 0 && args->args_count != 1) ||
 310             (phy->id == 1 && args->args_count != 2)) {
 311                 dev_err(dev, "invalid number of cells for phy port%ld\n",
 312                         phy->id);
 313                 return -EINVAL;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static const struct phy_ops stm32_usbphyc_phy_ops = {
 320         .init = stm32_usbphyc_phy_init,
 321         .exit = stm32_usbphyc_phy_exit,
 322         .power_on = stm32_usbphyc_phy_power_on,
 323         .power_off = stm32_usbphyc_phy_power_off,
 324         .of_xlate = stm32_usbphyc_of_xlate,
 325 };
 326
 327 static int stm32_usbphyc_probe(struct udevice *dev)
 328 {
 329         struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
 330         struct reset_ctl reset;
 331         ofnode node;
 332         int i, ret;
 333
 334         usbphyc->base = dev_read_addr(dev);
 335         if (usbphyc->base == FDT_ADDR_T_NONE)
 336                 return -EINVAL;
 337
 338         /* Enable clock */
 339         ret = clk_get_by_index(dev, 0, &usbphyc->clk);
 340         if (ret)
 341                 return ret;
 342
 343         ret = clk_enable(&usbphyc->clk);
 344         if (ret)
 345                 return ret;
 346
 347         /* Reset */
 348         ret = reset_get_by_index(dev, 0, &reset);
 349         if (!ret) {
 350                 reset_assert(&reset);
 351                 udelay(2);
 352                 reset_deassert(&reset);
 353         }
 354
 355         /* get usbphyc regulator */
 356         ret = device_get_supply_regulator(dev, "vdda1v1-supply",
 357                                           &usbphyc->vdda1v1);
 358         if (ret) {
 359                 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
 360                 return ret;
 361         }
 362
 363         ret = device_get_supply_regulator(dev, "vdda1v8-supply",
 364                                           &usbphyc->vdda1v8);
 365         if (ret) {
 366                 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
 367                 return ret;
 368         }
 369
 370         /*
 371          * parse all PHY subnodes in order to populate regulator associated
 372          * to each PHY port
 373          */
 374         node = dev_read_first_subnode(dev);
 375         for (i = 0; i < MAX_PHYS; i++) {
 376                 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
 377
 378                 usbphyc_phy->init = false;
 379                 usbphyc_phy->powered = false;
 380                 ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
 381                                                   &usbphyc_phy->vdd);
 382                 if (ret)
 383                         return ret;
 384
 385                 node = dev_read_next_subnode(node);
 386         }
 387
 388         /* Check if second port has to be used for host controller */
 389         if (dev_read_bool(dev, "st,port2-switch-to-host"))
 390                 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
 391
 392         return 0;
 393 }
 394
 395 static const struct udevice_id stm32_usbphyc_of_match[] = {
 396         { .compatible = "st,stm32mp1-usbphyc", },
 397         { },
 398 };
 399
 400 U_BOOT_DRIVER(stm32_usb_phyc) = {
 401         .name = "stm32-usbphyc",
 402         .id = UCLASS_PHY,
 403         .of_match = stm32_usbphyc_of_match,
 404         .ops = &stm32_usbphyc_phy_ops,
 405         .probe = stm32_usbphyc_probe,
 406         .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),
 407 };