1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 - 2019 MediaTek Inc.
4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
11 #include <generic-phy.h>
15 #include <dm/device_compat.h>
16 #include <dm/devres.h>
18 #include <dt-bindings/phy/phy.h>
20 /* version V1 sub-banks offset base address */
21 /* banks shared by multiple phys */
22 #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
23 #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
24 #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
26 #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
27 /* u3/pcie/sata phy banks */
28 #define SSUSB_SIFSLV_V1_U3PHYD 0x000
29 #define SSUSB_SIFSLV_V1_U3PHYA 0x200
31 /* version V2 sub-banks offset base address */
33 #define SSUSB_SIFSLV_V2_MISC 0x000
34 #define SSUSB_SIFSLV_V2_U2FREQ 0x100
35 #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
36 /* u3/pcie/sata phy banks */
37 #define SSUSB_SIFSLV_V2_SPLLC 0x000
38 #define SSUSB_SIFSLV_V2_CHIP 0x100
39 #define SSUSB_SIFSLV_V2_U3PHYD 0x200
40 #define SSUSB_SIFSLV_V2_U3PHYA 0x400
42 #define U3P_USBPHYACR0 0x000
43 #define PA0_RG_U2PLL_FORCE_ON BIT(15)
44 #define PA0_RG_USB20_INTR_EN BIT(5)
46 #define U3P_USBPHYACR5 0x014
47 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
48 #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
49 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
50 #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
52 #define U3P_USBPHYACR6 0x018
53 #define PA6_RG_U2_BC11_SW_EN BIT(23)
54 #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
55 #define PA6_RG_U2_SQTH GENMASK(3, 0)
56 #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
58 #define U3P_U2PHYACR4 0x020
59 #define P2C_RG_USB20_GPIO_CTL BIT(9)
60 #define P2C_USB20_GPIO_MODE BIT(8)
61 #define P2C_U2_GPIO_CTR_MSK \
62 (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
64 #define U3P_U2PHYDTM0 0x068
65 #define P2C_FORCE_UART_EN BIT(26)
66 #define P2C_FORCE_DATAIN BIT(23)
67 #define P2C_FORCE_DM_PULLDOWN BIT(21)
68 #define P2C_FORCE_DP_PULLDOWN BIT(20)
69 #define P2C_FORCE_XCVRSEL BIT(19)
70 #define P2C_FORCE_SUSPENDM BIT(18)
71 #define P2C_FORCE_TERMSEL BIT(17)
72 #define P2C_RG_DATAIN GENMASK(13, 10)
73 #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
74 #define P2C_RG_DMPULLDOWN BIT(7)
75 #define P2C_RG_DPPULLDOWN BIT(6)
76 #define P2C_RG_XCVRSEL GENMASK(5, 4)
77 #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
78 #define P2C_RG_SUSPENDM BIT(3)
79 #define P2C_RG_TERMSEL BIT(2)
80 #define P2C_DTM0_PART_MASK \
81 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
82 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
83 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
84 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
86 #define U3P_U2PHYDTM1 0x06C
87 #define P2C_RG_UART_EN BIT(16)
88 #define P2C_FORCE_IDDIG BIT(9)
89 #define P2C_RG_VBUSVALID BIT(5)
90 #define P2C_RG_SESSEND BIT(4)
91 #define P2C_RG_AVALID BIT(2)
92 #define P2C_RG_IDDIG BIT(1)
94 #define U3P_U3_CHIP_GPIO_CTLD 0x0c
95 #define P3C_REG_IP_SW_RST BIT(31)
96 #define P3C_MCU_BUS_CK_GATE_EN BIT(30)
97 #define P3C_FORCE_IP_SW_RST BIT(29)
99 #define U3P_U3_CHIP_GPIO_CTLE 0x10
100 #define P3C_RG_SWRST_U3_PHYD BIT(25)
101 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
103 #define U3P_U3_PHYA_REG0 0x000
104 #define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
105 #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
107 #define U3P_U3_PHYA_REG1 0x004
108 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
109 #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
111 #define U3P_U3_PHYA_REG6 0x018
112 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
113 #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
115 #define U3P_U3_PHYA_REG9 0x024
116 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
117 #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
119 #define U3P_U3_PHYA_DA_REG0 0x100
120 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
121 #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
122 #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
123 #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
124 #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
125 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
127 #define U3P_U3_PHYA_DA_REG4 0x108
128 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
129 #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
130 #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
132 #define U3P_U3_PHYA_DA_REG5 0x10c
133 #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
134 #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
135 #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
136 #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
138 #define U3P_U3_PHYA_DA_REG6 0x110
139 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
140 #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
142 #define U3P_U3_PHYA_DA_REG7 0x114
143 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
144 #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
146 #define U3P_U3_PHYA_DA_REG20 0x13c
147 #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
148 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
150 #define U3P_U3_PHYA_DA_REG25 0x148
151 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
152 #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
154 #define U3P_U3_PHYD_LFPS1 0x00c
155 #define P3D_RG_FWAKE_TH GENMASK(21, 16)
156 #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
158 #define U3P_U3_PHYD_CDR1 0x05c
159 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
160 #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
161 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
162 #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
164 #define U3P_U3_PHYD_RXDET1 0x128
165 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
166 #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
168 #define U3P_U3_PHYD_RXDET2 0x12c
169 #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
170 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
172 #define U3P_SPLLC_XTALCTL3 0x018
173 #define XC3_RG_U3_XTAL_RX_PWD BIT(9)
174 #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
176 enum mtk_phy_version {
190 void __iomem *phyd; /* include u3phyd_bank2 */
191 void __iomem *phya; /* include u3phya_da */
194 struct mtk_phy_instance {
195 void __iomem *port_base;
196 const struct device_node *np;
198 struct u2phy_banks u2_banks;
199 struct u3phy_banks u3_banks;
202 struct clk ref_clk; /* reference clock of (digital) phy */
203 struct clk da_ref_clk; /* reference clock of analog phy */
210 void __iomem *sif_base;
211 enum mtk_phy_version version;
212 struct mtk_phy_instance **phys;
216 static void u2_phy_instance_init(struct mtk_tphy *tphy,
217 struct mtk_phy_instance *instance)
219 struct u2phy_banks *u2_banks = &instance->u2_banks;
221 /* switch to USB function, and enable usb pll */
222 clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
223 P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
224 P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
226 clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
227 setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
229 /* disable switch 100uA current to SSUSB */
230 clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
232 clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
234 /* DP/DM BC1.1 path Disable */
235 clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
236 PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
237 PA6_RG_U2_SQTH_VAL(2));
239 /* set HS slew rate */
240 clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
241 PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
243 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
246 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
247 struct mtk_phy_instance *instance)
249 struct u2phy_banks *u2_banks = &instance->u2_banks;
251 clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
252 P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
255 setbits_le32(u2_banks->com + U3P_USBPHYACR6,
256 PA6_RG_U2_OTG_VBUSCMP_EN);
258 clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
259 P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
261 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
264 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
265 struct mtk_phy_instance *instance)
267 struct u2phy_banks *u2_banks = &instance->u2_banks;
269 clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
270 P2C_RG_XCVRSEL | P2C_RG_DATAIN);
273 clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
274 PA6_RG_U2_OTG_VBUSCMP_EN);
276 clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
277 P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);
279 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
282 static void u3_phy_instance_init(struct mtk_tphy *tphy,
283 struct mtk_phy_instance *instance)
285 struct u3phy_banks *u3_banks = &instance->u3_banks;
287 /* gating PCIe Analog XTAL clock */
288 setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
289 XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
292 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
293 P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
295 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
296 P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
298 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
299 P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
301 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
302 P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
303 P3D_RG_CDR_BIR_LTD0_VAL(0xc) |
304 P3D_RG_CDR_BIR_LTD1_VAL(0x3));
306 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
307 P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
309 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
310 P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
312 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
313 P3D_RG_RXDET_STB2_SET_P3,
314 P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
316 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
319 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
320 struct mtk_phy_instance *instance)
322 struct u3phy_banks *u3_banks = &instance->u3_banks;
324 if (tphy->version != MTK_TPHY_V1)
327 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
328 P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
329 P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
330 P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
333 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
334 P3A_RG_CLKDRV_AMP_VAL(0x4));
335 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
336 P3A_RG_CLKDRV_OFF_VAL(0x1));
338 /* SSC delta -5000ppm */
339 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
340 P3A_RG_PLL_DELTA1_PE2H,
341 P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
343 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
344 P3A_RG_PLL_DELTA_PE2H,
345 P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
347 /* change pll BW 0.6M */
348 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
349 P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
350 P3A_RG_PLL_BR_PE2H_VAL(0x1) |
351 P3A_RG_PLL_IC_PE2H_VAL(0x1));
352 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
353 P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
354 P3A_RG_PLL_BC_PE2H_VAL(0x3));
356 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
357 P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
358 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
359 P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
361 /* Tx Detect Rx Timing: 10us -> 5us */
362 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
363 P3D_RG_RXDET_STB2_SET,
364 P3D_RG_RXDET_STB2_SET_VAL(0x10));
365 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
366 P3D_RG_RXDET_STB2_SET_P3,
367 P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
369 /* wait for PCIe subsys register to active */
373 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
374 struct mtk_phy_instance *instance)
376 struct u3phy_banks *bank = &instance->u3_banks;
378 clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
379 P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
380 clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
381 P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
384 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
385 struct mtk_phy_instance *instance)
388 struct u3phy_banks *bank = &instance->u3_banks;
390 setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
391 P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
392 setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
393 P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
396 static void phy_v1_banks_init(struct mtk_tphy *tphy,
397 struct mtk_phy_instance *instance)
399 struct u2phy_banks *u2_banks = &instance->u2_banks;
400 struct u3phy_banks *u3_banks = &instance->u3_banks;
402 switch (instance->type) {
404 u2_banks->misc = NULL;
405 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
406 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
410 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
411 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
412 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
413 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
416 dev_err(tphy->dev, "incompatible PHY type\n");
421 static void phy_v2_banks_init(struct mtk_tphy *tphy,
422 struct mtk_phy_instance *instance)
424 struct u2phy_banks *u2_banks = &instance->u2_banks;
425 struct u3phy_banks *u3_banks = &instance->u3_banks;
427 switch (instance->type) {
429 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
430 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
431 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
435 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
436 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
437 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
438 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
441 dev_err(tphy->dev, "incompatible PHY type\n");
446 static int mtk_phy_init(struct phy *phy)
448 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
449 struct mtk_phy_instance *instance = tphy->phys[phy->id];
452 ret = clk_enable(&instance->ref_clk);
454 dev_err(tphy->dev, "failed to enable ref_clk\n");
458 ret = clk_enable(&instance->da_ref_clk);
460 dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret);
461 clk_disable(&instance->ref_clk);
465 switch (instance->type) {
467 u2_phy_instance_init(tphy, instance);
470 u3_phy_instance_init(tphy, instance);
473 pcie_phy_instance_init(tphy, instance);
476 dev_err(tphy->dev, "incompatible PHY type\n");
483 static int mtk_phy_power_on(struct phy *phy)
485 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
486 struct mtk_phy_instance *instance = tphy->phys[phy->id];
488 if (instance->type == PHY_TYPE_USB2)
489 u2_phy_instance_power_on(tphy, instance);
490 else if (instance->type == PHY_TYPE_PCIE)
491 pcie_phy_instance_power_on(tphy, instance);
496 static int mtk_phy_power_off(struct phy *phy)
498 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
499 struct mtk_phy_instance *instance = tphy->phys[phy->id];
501 if (instance->type == PHY_TYPE_USB2)
502 u2_phy_instance_power_off(tphy, instance);
503 else if (instance->type == PHY_TYPE_PCIE)
504 pcie_phy_instance_power_off(tphy, instance);
509 static int mtk_phy_exit(struct phy *phy)
511 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
512 struct mtk_phy_instance *instance = tphy->phys[phy->id];
514 clk_disable(&instance->da_ref_clk);
515 clk_disable(&instance->ref_clk);
520 static int mtk_phy_xlate(struct phy *phy,
521 struct ofnode_phandle_args *args)
523 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
524 struct mtk_phy_instance *instance = NULL;
525 const struct device_node *phy_np = ofnode_to_np(args->node);
529 dev_err(phy->dev, "null pointer phy node\n");
533 if (args->args_count < 1) {
534 dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
538 for (index = 0; index < tphy->nphys; index++)
539 if (phy_np == tphy->phys[index]->np) {
540 instance = tphy->phys[index];
545 dev_err(phy->dev, "failed to find appropriate phy\n");
550 instance->type = args->args[1];
551 if (!(instance->type == PHY_TYPE_USB2 ||
552 instance->type == PHY_TYPE_USB3 ||
553 instance->type == PHY_TYPE_PCIE)) {
554 dev_err(phy->dev, "unsupported device type\n");
558 if (tphy->version == MTK_TPHY_V1) {
559 phy_v1_banks_init(tphy, instance);
560 } else if (tphy->version == MTK_TPHY_V2) {
561 phy_v2_banks_init(tphy, instance);
563 dev_err(phy->dev, "phy version is not supported\n");
570 static const struct phy_ops mtk_tphy_ops = {
571 .init = mtk_phy_init,
572 .exit = mtk_phy_exit,
573 .power_on = mtk_phy_power_on,
574 .power_off = mtk_phy_power_off,
575 .of_xlate = mtk_phy_xlate,
578 static int mtk_tphy_probe(struct udevice *dev)
580 struct mtk_tphy *tphy = dev_get_priv(dev);
584 tphy->nphys = dev_get_child_count(dev);
586 tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
592 tphy->version = dev_get_driver_data(dev);
594 /* v1 has shared banks */
595 if (tphy->version == MTK_TPHY_V1) {
596 tphy->sif_base = dev_read_addr_ptr(dev);
601 dev_for_each_subnode(subnode, dev) {
602 struct mtk_phy_instance *instance;
606 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
610 addr = ofnode_get_addr(subnode);
611 if (addr == FDT_ADDR_T_NONE)
614 instance->port_base = map_sysmem(addr, 0);
615 instance->index = index;
616 instance->np = ofnode_to_np(subnode);
617 tphy->phys[index] = instance;
620 err = clk_get_optional_nodev(subnode, "ref",
625 err = clk_get_optional_nodev(subnode, "da_ref",
626 &instance->da_ref_clk);
634 static const struct udevice_id mtk_tphy_id_table[] = {
635 { .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
636 { .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
640 U_BOOT_DRIVER(mtk_tphy) = {
643 .of_match = mtk_tphy_id_table,
644 .ops = &mtk_tphy_ops,
645 .probe = mtk_tphy_probe,
646 .priv_auto_alloc_size = sizeof(struct mtk_tphy),