1 // SPDX-License-Identifier: GPL-2.0+
3 * Meson8, Meson8b and GXBB USB2 PHY driver
5 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 * Copyright (C) 2018 BayLibre, SAS
8 * Author: Beniamino Galvani <b.galvani@gmail.com>
14 #include <generic-phy.h>
15 #include <power/regulator.h>
19 #define REG_CONFIG 0x00
20 #define REG_CONFIG_CLK_EN BIT(0)
21 #define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)
22 #define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4)
23 #define REG_CONFIG_CLK_32k_ALTSEL BIT(15)
24 #define REG_CONFIG_TEST_TRIG BIT(31)
27 #define REG_CTRL_SOFT_PRST BIT(0)
28 #define REG_CTRL_SOFT_HRESET BIT(1)
29 #define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2)
30 #define REG_CTRL_CLK_DET_RST BIT(4)
31 #define REG_CTRL_INTR_SEL BIT(5)
32 #define REG_CTRL_CLK_DETECTED BIT(8)
33 #define REG_CTRL_SOF_SENT_RCVD_TGL BIT(9)
34 #define REG_CTRL_SOF_TOGGLE_OUT BIT(10)
35 #define REG_CTRL_POWER_ON_RESET BIT(15)
36 #define REG_CTRL_SLEEPM BIT(16)
37 #define REG_CTRL_TX_BITSTUFF_ENN_H BIT(17)
38 #define REG_CTRL_TX_BITSTUFF_ENN BIT(18)
39 #define REG_CTRL_COMMON_ON BIT(19)
40 #define REG_CTRL_REF_CLK_SEL_MASK GENMASK(21, 20)
41 #define REG_CTRL_REF_CLK_SEL_SHIFT 20
42 #define REG_CTRL_FSEL_MASK GENMASK(24, 22)
43 #define REG_CTRL_FSEL_SHIFT 22
44 #define REG_CTRL_PORT_RESET BIT(25)
45 #define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26)
47 /* bits [31:26], [24:21] and [15:3] seem to be read-only */
48 #define REG_ADP_BC 0x0c
49 #define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0)
50 #define REG_ADP_BC_VBUS_VLD_EXT BIT(1)
51 #define REG_ADP_BC_OTG_DISABLE BIT(2)
52 #define REG_ADP_BC_ID_PULLUP BIT(3)
53 #define REG_ADP_BC_DRV_VBUS BIT(4)
54 #define REG_ADP_BC_ADP_PRB_EN BIT(5)
55 #define REG_ADP_BC_ADP_DISCHARGE BIT(6)
56 #define REG_ADP_BC_ADP_CHARGE BIT(7)
57 #define REG_ADP_BC_SESS_END BIT(8)
58 #define REG_ADP_BC_DEVICE_SESS_VLD BIT(9)
59 #define REG_ADP_BC_B_VALID BIT(10)
60 #define REG_ADP_BC_A_VALID BIT(11)
61 #define REG_ADP_BC_ID_DIG BIT(12)
62 #define REG_ADP_BC_VBUS_VALID BIT(13)
63 #define REG_ADP_BC_ADP_PROBE BIT(14)
64 #define REG_ADP_BC_ADP_SENSE BIT(15)
65 #define REG_ADP_BC_ACA_ENABLE BIT(16)
66 #define REG_ADP_BC_DCD_ENABLE BIT(17)
67 #define REG_ADP_BC_VDAT_DET_EN_B BIT(18)
68 #define REG_ADP_BC_VDAT_SRC_EN_B BIT(19)
69 #define REG_ADP_BC_CHARGE_SEL BIT(20)
70 #define REG_ADP_BC_CHARGE_DETECT BIT(21)
71 #define REG_ADP_BC_ACA_PIN_RANGE_C BIT(22)
72 #define REG_ADP_BC_ACA_PIN_RANGE_B BIT(23)
73 #define REG_ADP_BC_ACA_PIN_RANGE_A BIT(24)
74 #define REG_ADP_BC_ACA_PIN_GND BIT(25)
75 #define REG_ADP_BC_ACA_PIN_FLOAT BIT(26)
77 #define RESET_COMPLETE_TIME 500
78 #define ACA_ENABLE_COMPLETE_TIME 50
80 struct phy_meson_gxbb_usb2_priv {
81 struct regmap *regmap;
82 struct reset_ctl_bulk resets;
83 #if CONFIG_IS_ENABLED(DM_REGULATOR)
84 struct udevice *phy_supply;
88 static int phy_meson_gxbb_usb2_power_on(struct phy *phy)
90 struct udevice *dev = phy->dev;
91 struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
94 #if CONFIG_IS_ENABLED(DM_REGULATOR)
95 if (priv->phy_supply) {
96 int ret = regulator_set_enable(priv->phy_supply, true);
103 regmap_update_bits(priv->regmap, REG_CONFIG,
104 REG_CONFIG_CLK_32k_ALTSEL,
105 REG_CONFIG_CLK_32k_ALTSEL);
106 regmap_update_bits(priv->regmap, REG_CTRL,
107 REG_CTRL_REF_CLK_SEL_MASK,
108 0x2 << REG_CTRL_REF_CLK_SEL_SHIFT);
109 regmap_update_bits(priv->regmap, REG_CTRL,
111 0x5 << REG_CTRL_FSEL_SHIFT);
114 regmap_update_bits(priv->regmap, REG_CTRL,
115 REG_CTRL_POWER_ON_RESET,
116 REG_CTRL_POWER_ON_RESET);
117 udelay(RESET_COMPLETE_TIME);
118 regmap_update_bits(priv->regmap, REG_CTRL,
119 REG_CTRL_POWER_ON_RESET,
121 udelay(RESET_COMPLETE_TIME);
123 regmap_update_bits(priv->regmap, REG_CTRL,
124 REG_CTRL_SOF_TOGGLE_OUT,
125 REG_CTRL_SOF_TOGGLE_OUT);
128 regmap_update_bits(priv->regmap, REG_ADP_BC,
129 REG_ADP_BC_ACA_ENABLE,
130 REG_ADP_BC_ACA_ENABLE);
131 udelay(ACA_ENABLE_COMPLETE_TIME);
133 regmap_read(priv->regmap, REG_ADP_BC, &val);
134 if (val & REG_ADP_BC_ACA_PIN_FLOAT) {
135 pr_err("Error powering on GXBB USB PHY\n");
142 static int phy_meson_gxbb_usb2_power_off(struct phy *phy)
144 #if CONFIG_IS_ENABLED(DM_REGULATOR)
145 struct udevice *dev = phy->dev;
146 struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
148 if (priv->phy_supply) {
149 int ret = regulator_set_enable(priv->phy_supply, false);
159 static struct phy_ops meson_gxbb_usb2_phy_ops = {
160 .power_on = phy_meson_gxbb_usb2_power_on,
161 .power_off = phy_meson_gxbb_usb2_power_off,
164 static int meson_gxbb_usb2_phy_probe(struct udevice *dev)
166 struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
167 struct clk clk_usb_general, clk_usb;
170 ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
174 ret = clk_get_by_name(dev, "usb_general", &clk_usb_general);
178 ret = clk_enable(&clk_usb_general);
179 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
180 pr_err("Failed to enable PHY general clock\n");
184 ret = clk_get_by_name(dev, "usb", &clk_usb);
188 ret = clk_enable(&clk_usb);
189 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
190 pr_err("Failed to enable PHY clock\n");
194 #if CONFIG_IS_ENABLED(DM_REGULATOR)
195 ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
196 if (ret && ret != -ENOENT) {
197 pr_err("Failed to get PHY regulator\n");
201 ret = reset_get_bulk(dev, &priv->resets);
203 ret = reset_deassert_bulk(&priv->resets);
205 pr_err("Failed to deassert reset\n");
213 static int meson_gxbb_usb2_phy_remove(struct udevice *dev)
215 struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
217 return reset_release_bulk(&priv->resets);
220 static const struct udevice_id meson_gxbb_usb2_phy_ids[] = {
221 { .compatible = "amlogic,meson8-usb2-phy" },
222 { .compatible = "amlogic,meson8b-usb2-phy" },
223 { .compatible = "amlogic,meson-gxbb-usb2-phy" },
227 U_BOOT_DRIVER(meson_gxbb_usb2_phy) = {
228 .name = "meson_gxbb_usb2_phy",
230 .of_match = meson_gxbb_usb2_phy_ids,
231 .probe = meson_gxbb_usb2_phy_probe,
232 .remove = meson_gxbb_usb2_phy_remove,
233 .ops = &meson_gxbb_usb2_phy_ops,
234 .priv_auto_alloc_size = sizeof(struct phy_meson_gxbb_usb2_priv),