1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Marvell International Ltd.
6 #ifndef _COMPHY_A3700_H_
7 #define _COMPHY_A3700_H_
9 #include "comphy_core.h"
10 #include "comphy_hpipe.h"
12 #define MVEBU_REG(offs) \
13 ((void __iomem *)(ulong)MVEBU_REGISTER(offs))
15 #define DEFAULT_REFCLK_MHZ 25
16 #define PLL_SET_DELAY_US 600
17 #define PLL_LOCK_TIMEOUT 1000
18 #define POLL_16B_REG 1
19 #define POLL_32B_REG 0
22 * COMPHY SB definitions
24 #define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC)
26 #define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (1 - lane) * 0x28)
27 #define rb_pin_pu_iveref BIT(1)
28 #define rb_pin_reset_core BIT(11)
29 #define rb_pin_reset_comphy BIT(12)
30 #define rb_pin_pu_pll BIT(16)
31 #define rb_pin_pu_rx BIT(17)
32 #define rb_pin_pu_tx BIT(18)
33 #define rb_pin_tx_idle BIT(19)
34 #define rf_gen_rx_sel_shift 22
35 #define rf_gen_rx_select (0x0F << rf_gen_rx_sel_shift)
36 #define rf_gen_tx_sel_shift 26
37 #define rf_gen_tx_select (0x0F << rf_gen_tx_sel_shift)
38 #define rb_phy_rx_init BIT(30)
40 #define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (1 - lane) * 0x28)
41 #define rb_rx_init_done BIT(0)
42 #define rb_pll_ready_rx BIT(2)
43 #define rb_pll_ready_tx BIT(3)
46 * PCIe/USB/SGMII definitions
48 #define PCIE_BASE MVEBU_REG(0x070000)
49 #define PCIETOP_BASE MVEBU_REG(0x080000)
50 #define PCIE_RAMBASE MVEBU_REG(0x08C000)
51 #define PCIEPHY_BASE MVEBU_REG(0x01F000)
52 #define PCIEPHY_SHFT 2
54 #define USB32_BASE MVEBU_REG(0x050000) /* usb3 device */
55 #define USB32H_BASE MVEBU_REG(0x058000) /* usb3 host */
56 #define USB3PHY_BASE MVEBU_REG(0x05C000)
57 #define USB2PHY_BASE MVEBU_REG(0x05D000)
58 #define USB2PHY2_BASE MVEBU_REG(0x05F000)
59 #define USB32_CTRL_BASE MVEBU_REG(0x05D800)
60 #define USB3PHY_SHFT 2
61 #define USB3PHY_LANE2_REG_BASE_OFFSET 0x200
63 static inline void __iomem *sgmiiphy_addr(u32 lane, u32 addr)
65 addr = (addr & 0x00007FF) * 2;
67 return PCIEPHY_BASE + addr;
69 return USB3PHY_BASE + addr;
78 static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr)
81 return PCIEPHY_BASE + addr * PCIEPHY_SHFT;
83 return USB3PHY_BASE + addr * USB3PHY_SHFT;
86 /* bit definition for USB32_CTRL_BASE (USB32 Control Mode) */
87 #define usb32_ctrl_id_mode BIT(0)
88 #define usb32_ctrl_soft_id BIT(1)
89 #define usb32_ctrl_int_mode BIT(4)
91 #define PWR_PLL_CTRL 0x01
92 #define rf_phy_mode_shift 5
93 #define rf_phy_mode_mask (0x7 << rf_phy_mode_shift)
94 #define rf_ref_freq_sel_shift 0
95 #define rf_ref_freq_sel_mask (0x1F << rf_ref_freq_sel_shift)
96 #define PHY_MODE_SGMII 0x4
98 #define KVCO_CAL_CTRL 0x02
99 #define rb_use_max_pll_rate BIT(12)
100 #define rb_force_calibration_done BIT(9)
102 #define DIG_LB_EN 0x23
103 #define rf_data_width_shift 10
104 #define rf_data_width_mask (0x3 << rf_data_width_shift)
106 #define SYNC_PATTERN 0x24
107 #define phy_txd_inv BIT(10)
108 #define phy_rxd_inv BIT(11)
110 #define SYNC_MASK_GEN 0x25
111 #define rb_idle_sync_en BIT(12)
113 #define UNIT_CTRL 0x48
115 #define GEN2_SETTINGS_2 0x3e
116 #define g2_tx_ssc_amp BIT(14)
118 #define GEN2_SETTINGS_3 0x3f
120 #define GEN3_SETTINGS_3 0x112
122 #define MISC_REG0 0x4f
123 #define rb_clk100m_125m_en BIT(4)
124 #define rb_clk500m_en BIT(7)
125 #define rb_ref_clk_sel BIT(10)
127 #define UNIT_IFACE_REF_CLK_CTRL 0x51
128 #define rb_ref1m_gen_div_force BIT(8)
129 #define rf_ref1m_gen_div_value_shift 0
130 #define rf_ref1m_gen_div_value_mask (0xFF << rf_ref1m_gen_div_value_shift)
132 #define UNIT_ERR_CNT_CONST_CTRL 0x6a
133 #define rb_fast_dfe_enable BIT(13)
135 #define MISC_REG1 0x73
136 #define bf_sel_bits_pcie_force BIT(15)
138 #define LANE_CFG0 0x180
139 #define bf_use_max_pll_rate BIT(9)
141 #define LANE_CFG1 0x181
142 #define bf_use_max_pll_rate BIT(9)
143 #define prd_txdeemph1_mask BIT(15)
144 #define tx_det_rx_mode BIT(6)
145 #define gen2_tx_data_dly_deft (2 << 3)
146 #define gen2_tx_data_dly_mask (BIT(3) | BIT(4))
147 #define tx_elec_idle_mode_en BIT(0)
149 #define LANE_CFG4 0x188
150 #define bf_spread_spectrum_clock_en BIT(7)
152 #define LANE_STAT1 0x183
153 #define rb_txdclk_pclk_en BIT(0)
155 #define GLOB_PHY_CTRL0 0x1c1
156 #define bf_soft_rst BIT(0)
157 #define bf_mode_refdiv 0x30
158 #define rb_mode_core_clk_freq_sel BIT(9)
159 #define rb_mode_pipe_width_32 BIT(3)
161 #define TEST_MODE_CTRL 0x1c2
162 #define rb_mode_margin_override BIT(2)
164 #define GLOB_CLK_SRC_LO 0x1c3
165 #define bf_cfg_sel_20b BIT(15)
167 #define PWR_MGM_TIM1 0x1d0
169 #define PCIE_REF_CLK_ADDR (PCIE_BASE + 0x4814)
171 #define USB3_CTRPUL_VAL_REG (0x20 + USB32_BASE)
172 #define USB3H_CTRPUL_VAL_REG (0x3454 + USB32H_BASE)
173 #define rb_usb3_ctr_100ns 0xff000000
175 #define USB2_OTG_PHY_CTRL_ADDR (0x820 + USB2PHY_BASE)
176 #define rb_usb2phy_suspm BIT(14)
177 #define rb_usb2phy_pu BIT(0)
179 #define USB2_PHY_OTG_CTRL_ADDR (0x34 + USB2PHY_BASE)
180 #define rb_pu_otg BIT(4)
182 #define USB2_PHY_CHRGR_DET_ADDR (0x38 + USB2PHY_BASE)
183 #define rb_cdp_en BIT(2)
184 #define rb_dcp_en BIT(3)
185 #define rb_pd_en BIT(4)
186 #define rb_pu_chrg_dtc BIT(5)
187 #define rb_cdp_dm_auto BIT(7)
188 #define rb_enswitch_dp BIT(12)
189 #define rb_enswitch_dm BIT(13)
191 #define USB2_CAL_CTRL_ADDR (0x8 + USB2PHY_BASE)
192 #define rb_usb2phy_pllcal_done BIT(31)
193 #define rb_usb2phy_impcal_done BIT(23)
195 #define USB2_PLL_CTRL0_ADDR (0x0 + USB2PHY_BASE)
196 #define rb_usb2phy_pll_ready BIT(31)
198 #define USB2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY_BASE)
199 #define rb_usb2phy_sqcal_done BIT(31)
201 #define USB2_PHY2_CTRL_ADDR (0x804 + USB2PHY2_BASE)
202 #define rb_usb2phy2_suspm BIT(7)
203 #define rb_usb2phy2_pu BIT(0)
204 #define USB2_PHY2_CAL_CTRL_ADDR (0x8 + USB2PHY2_BASE)
205 #define USB2_PHY2_PLL_CTRL0_ADDR (0x0 + USB2PHY2_BASE)
206 #define USB2_PHY2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY2_BASE)
208 #define USB2_PHY_BASE(usb32) (usb32 == 0 ? USB2PHY2_BASE : USB2PHY_BASE)
209 #define USB2_PHY_CTRL_ADDR(usb32) \
210 (usb32 == 0 ? USB2_PHY2_CTRL_ADDR : USB2_OTG_PHY_CTRL_ADDR)
211 #define RB_USB2PHY_SUSPM(usb32) \
212 (usb32 == 0 ? rb_usb2phy2_suspm : rb_usb2phy_suspm)
213 #define RB_USB2PHY_PU(usb32) \
214 (usb32 == 0 ? rb_usb2phy2_pu : rb_usb2phy_pu)
215 #define USB2_PHY_CAL_CTRL_ADDR(usb32) \
216 (usb32 == 0 ? USB2_PHY2_CAL_CTRL_ADDR : USB2_CAL_CTRL_ADDR)
217 #define USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32) \
218 (usb32 == 0 ? USB2_PHY2_RX_CHAN_CTRL1_ADDR : USB2_RX_CHAN_CTRL1_ADDR)
219 #define USB2_PHY_PLL_CTRL0_ADDR(usb32) \
220 (usb32 == 0 ? USB2_PHY2_PLL_CTRL0_ADDR : USB2_PLL_CTRL0_ADDR)
225 #define AHCI_BASE MVEBU_REG(0xE0000)
227 #define rh_vsreg_addr (AHCI_BASE + 0x178)
228 #define rh_vsreg_data (AHCI_BASE + 0x17C)
229 #define rh_vs0_a (AHCI_BASE + 0xA0)
230 #define rh_vs0_d (AHCI_BASE + 0xA4)
232 #define vphy_sync_pattern_reg 0x224
233 #define bs_txd_inv BIT(10)
234 #define bs_rxd_inv BIT(11)
236 #define vphy_loopback_reg0 0x223
237 #define bs_phyintf_40bit 0x0C00
238 #define bs_pll_ready_tx 0x10
240 #define vphy_power_reg0 0x201
242 #define vphy_calctl_reg 0x202
243 #define bs_max_pll_rate BIT(12)
245 #define vphy_reserve_reg 0x0e
246 #define bs_phyctrl_frm_pin BIT(13)
248 #define vsata_ctrl_reg 0x00
249 #define bs_phy_pu_pll BIT(6)
252 * SDIO/eMMC definitions
254 #define SDIO_BASE MVEBU_REG(0xD8000)
256 #define SDIO_HOST_CTRL1_ADDR (SDIO_BASE + 0x28)
257 #define SDIO_SDHC_FIFO_ADDR (SDIO_BASE + 0x12C)
258 #define SDIO_CAP_12_ADDR (SDIO_BASE + 0x40)
259 #define SDIO_ENDIAN_ADDR (SDIO_BASE + 0x1A4)
260 #define SDIO_PHY_TIMING_ADDR (SDIO_BASE + 0x170)
261 #define SDIO_PHY_PAD_CTRL0_ADDR (SDIO_BASE + 0x178)
262 #define SDIO_DLL_RST_ADDR (SDIO_BASE + 0x148)
264 #endif /* _COMPHY_A3700_H_ */