1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
5 * Derived from linux/arch/mips/bcm63xx/usb-common.c:
6 * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright 2013 Florian Fainelli <florian@openwrt.org>
13 #include <generic-phy.h>
16 #include <power-domain.h>
19 #include <dm/device.h>
21 /* USBH PLL Control register */
22 #define USBH_PLL_REG 0x18
23 #define USBH_PLL_IDDQ_PWRDN BIT(9)
24 #define USBH_PLL_PWRDN_DELAY BIT(10)
26 /* USBH Swap Control register */
27 #define USBH_SWAP_REG 0x1c
28 #define USBH_SWAP_OHCI_DATA BIT(0)
29 #define USBH_SWAP_OHCI_ENDIAN BIT(1)
30 #define USBH_SWAP_EHCI_DATA BIT(3)
31 #define USBH_SWAP_EHCI_ENDIAN BIT(4)
33 /* USBH Setup register */
34 #define USBH_SETUP_REG 0x28
35 #define USBH_SETUP_IOC BIT(4)
36 #define USBH_SETUP_IPP BIT(5)
38 struct bcm6368_usbh_hw {
43 struct bcm6368_usbh_priv {
44 const struct bcm6368_usbh_hw *hw;
48 static int bcm6368_usbh_init(struct phy *phy)
50 struct bcm6368_usbh_priv *priv = dev_get_priv(phy->dev);
51 const struct bcm6368_usbh_hw *hw = priv->hw;
53 /* configure to work in native cpu endian */
54 clrsetbits_be32(priv->regs + USBH_SWAP_REG,
55 USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
56 USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
60 clrbits_be32(priv->regs + USBH_SETUP_REG, hw->setup_clr);
62 setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
64 /* enable pll control */
66 clrbits_be32(priv->regs + USBH_PLL_REG, hw->pll_clr);
71 static struct phy_ops bcm6368_usbh_ops = {
72 .init = bcm6368_usbh_init,
75 static const struct bcm6368_usbh_hw bcm6328_hw = {
76 .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
80 static const struct bcm6368_usbh_hw bcm6362_hw = {
85 static const struct bcm6368_usbh_hw bcm6368_hw = {
90 static const struct bcm6368_usbh_hw bcm63268_hw = {
91 .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
92 .setup_clr = USBH_SETUP_IPP,
95 static const struct udevice_id bcm6368_usbh_ids[] = {
97 .compatible = "brcm,bcm6328-usbh",
98 .data = (ulong)&bcm6328_hw,
100 .compatible = "brcm,bcm6362-usbh",
101 .data = (ulong)&bcm6362_hw,
103 .compatible = "brcm,bcm6368-usbh",
104 .data = (ulong)&bcm6368_hw,
106 .compatible = "brcm,bcm63268-usbh",
107 .data = (ulong)&bcm63268_hw,
108 }, { /* sentinel */ }
111 static int bcm6368_usbh_probe(struct udevice *dev)
113 struct bcm6368_usbh_priv *priv = dev_get_priv(dev);
114 const struct bcm6368_usbh_hw *hw =
115 (const struct bcm6368_usbh_hw *)dev_get_driver_data(dev);
116 #if defined(CONFIG_POWER_DOMAIN)
117 struct power_domain pwr_dom;
119 struct reset_ctl rst_ctl;
123 priv->regs = dev_remap_addr(dev);
129 /* enable usbh clock */
130 ret = clk_get_by_name(dev, "usbh", &clk);
134 ret = clk_enable(&clk);
138 ret = clk_free(&clk);
142 #if defined(CONFIG_POWER_DOMAIN)
143 /* enable power domain */
144 ret = power_domain_get(dev, &pwr_dom);
148 ret = power_domain_on(&pwr_dom);
152 ret = power_domain_free(&pwr_dom);
158 ret = reset_get_by_index(dev, 0, &rst_ctl);
162 ret = reset_deassert(&rst_ctl);
166 ret = reset_free(&rst_ctl);
170 /* enable usb_ref clock */
171 ret = clk_get_by_name(dev, "usb_ref", &clk);
173 ret = clk_enable(&clk);
177 ret = clk_free(&clk);
187 U_BOOT_DRIVER(bcm6368_usbh) = {
188 .name = "bcm6368-usbh",
190 .of_match = bcm6368_usbh_ids,
191 .ops = &bcm6368_usbh_ops,
192 .priv_auto_alloc_size = sizeof(struct bcm6368_usbh_priv),
193 .probe = bcm6368_usbh_probe,