2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
6 ********************************************************************
8 * Lots of code copied from:
10 * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
11 * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
12 * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
22 #include <pcmcia/ss.h>
23 #include <pcmcia/i82365.h>
24 #include <pcmcia/yenta.h>
26 #include <pcmcia/cirrus.h>
28 #include <pcmcia/ti113x.h>
31 static struct pci_device_id supported[] = {
33 {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
35 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
40 #define CYCLE_TIME 120
43 extern int SPD67290Init (void);
47 static void i82365_dump_regions (pci_dev_t dev);
50 typedef struct socket_info_t {
53 u_char pci_lat, cb_lat, sub_bus, cache;
60 cirrus_state_t c_state;
67 /* These definitions must match the pcic table! */
68 typedef enum pcic_id {
69 IS_PD6710, IS_PD672X, IS_VT83C469
72 typedef struct pcic_t {
76 static pcic_t pcic[] = {
83 static socket_info_t socket;
84 static socket_state_t state;
85 static struct pccard_mem_map mem;
86 static struct pccard_io_map io;
88 /*====================================================================*/
90 /* Some PCI shortcuts */
92 static int pci_readb (socket_info_t * s, int r, u_char * v)
94 return pci_read_config_byte (s->dev, r, v);
96 static int pci_writeb (socket_info_t * s, int r, u_char v)
98 return pci_write_config_byte (s->dev, r, v);
100 static int pci_readw (socket_info_t * s, int r, u_short * v)
102 return pci_read_config_word (s->dev, r, v);
104 static int pci_writew (socket_info_t * s, int r, u_short v)
106 return pci_write_config_word (s->dev, r, v);
109 static int pci_readl (socket_info_t * s, int r, u_int * v)
111 return pci_read_config_dword (s->dev, r, v);
113 static int pci_writel (socket_info_t * s, int r, u_int v)
115 return pci_write_config_dword (s->dev, r, v);
117 #endif /* !CONFIG_CPC45 */
119 /*====================================================================*/
123 #define cb_readb(s) readb((s)->cb_phys + 1)
124 #define cb_writeb(s, v) writeb(v, (s)->cb_phys)
125 #define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
126 #define cb_readl(s, r) readl((s)->cb_phys + (r))
127 #define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
130 static u_char i365_get (socket_info_t * s, u_short reg)
133 #ifdef CONFIG_PCMCIA_SLOT_A
139 val = I365_REG (slot, reg);
144 debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
148 static void i365_set (socket_info_t * s, u_short reg, u_char data)
150 #ifdef CONFIG_PCMCIA_SLOT_A
157 val = I365_REG (slot, reg);
160 cb_writeb2 (s, data);
162 debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
165 #else /* ! CONFIG_CPC45 */
167 #define cb_readb(s, r) readb((s)->cb_phys + (r))
168 #define cb_readl(s, r) readl((s)->cb_phys + (r))
169 #define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
170 #define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
172 static u_char i365_get (socket_info_t * s, u_short reg)
174 return cb_readb (s, 0x0800 + reg);
177 static void i365_set (socket_info_t * s, u_short reg, u_char data)
179 cb_writeb (s, 0x0800 + reg, data);
181 #endif /* CONFIG_CPC45 */
183 static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
185 i365_set (s, reg, i365_get (s, reg) | mask);
188 static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
190 i365_set (s, reg, i365_get (s, reg) & ~mask);
194 static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
196 u_char d = i365_get (s, reg);
198 i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
201 static u_short i365_get_pair (socket_info_t * s, u_short reg)
203 return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
205 #endif /* not used */
207 static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
209 i365_set (s, reg, data & 0xff);
210 i365_set (s, reg + 1, data >> 8);
214 /*======================================================================
216 Code to save and restore global state information for Cirrus
217 PD67xx controllers, and to set and report global configuration
220 ======================================================================*/
222 #define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
224 static void cirrus_get_state (socket_info_t * s)
227 cirrus_state_t *p = &s->c_state;
229 p->misc1 = i365_get (s, PD67_MISC_CTL_1);
230 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
231 p->misc2 = i365_get (s, PD67_MISC_CTL_2);
232 for (i = 0; i < 6; i++)
233 p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
237 static void cirrus_set_state (socket_info_t * s)
241 cirrus_state_t *p = &s->c_state;
243 misc = i365_get (s, PD67_MISC_CTL_2);
244 i365_set (s, PD67_MISC_CTL_2, p->misc2);
245 if (misc & PD67_MC2_SUSPEND)
247 misc = i365_get (s, PD67_MISC_CTL_1);
248 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
249 i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
250 for (i = 0; i < 6; i++)
251 i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
254 static u_int cirrus_set_opts (socket_info_t * s)
256 cirrus_state_t *p = &s->c_state;
262 flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
263 flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
265 if (p->misc2 & PD67_MC2_IRQ15_RI)
266 strcat (buf, " [ring]");
267 if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
268 strcat (buf, " [dyn mode]");
269 if (p->misc1 & PD67_MC1_INPACK_ENA)
270 strcat (buf, " [inpack]");
273 if (p->misc2 & PD67_MC2_IRQ15_RI)
277 strcat (buf, " [led]");
283 strcat (buf, " [dma]");
286 flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
288 if (p->misc2 & PD67_MC2_FREQ_BYPASS)
289 strcat (buf, " [freq bypass]");
294 p->timer[0] = p->timer[3] = setup_time;
296 p->timer[1] = cmd_time;
297 p->timer[4] = cmd_time * 2 + 4;
299 if (p->timer[1] == 0) {
302 if (p->timer[0] == 0)
303 p->timer[0] = p->timer[3] = 1;
306 p->timer[2] = p->timer[5] = recov_time;
308 debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
310 p->timer[0], p->timer[1], p->timer[2],
311 p->timer[3], p->timer[4], p->timer[5]);
316 #else /* !CONFIG_CPC45 */
318 /*======================================================================
320 Code to save and restore global state information for TI 1130 and
321 TI 1131 controllers, and to set and report global configuration
324 ======================================================================*/
326 static void ti113x_get_state (socket_info_t * s)
328 ti113x_state_t *p = &s->state;
330 pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
331 pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
332 pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
333 pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
334 pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
337 static void ti113x_set_state (socket_info_t * s)
339 ti113x_state_t *p = &s->state;
341 pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
342 pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
343 pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
344 pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
345 pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
346 pci_writel (s, TI12XX_IRQMUX, p->irqmux);
347 i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
348 i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
351 static u_int ti113x_set_opts (socket_info_t * s)
353 ti113x_state_t *p = &s->state;
356 p->cardctl &= ~TI113X_CCR_ZVENABLE;
357 p->cardctl |= TI113X_CCR_SPKROUTEN;
361 #endif /* CONFIG_CPC45 */
363 /*======================================================================
365 Routines to handle common CardBus options
367 ======================================================================*/
369 /* Default settings for PCI command configuration register */
370 #define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
371 PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
373 static void cb_get_state (socket_info_t * s)
375 pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
376 pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
377 pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
378 pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
379 pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
380 pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
383 static void cb_set_state (socket_info_t * s)
386 pci_writel (s, CB_LEGACY_MODE_BASE, 0);
387 pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
389 pci_writew (s, PCI_COMMAND, CMD_DFLT);
390 pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
391 pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
392 pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
393 pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
394 pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
395 pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
398 static void cb_set_opts (socket_info_t * s)
410 /*======================================================================
412 Power control for Cardbus controllers: used both for 16-bit and
415 ======================================================================*/
417 static int cb_set_power (socket_info_t * s, socket_state_t * state)
423 reg = I365_PWR_NORESET;
424 if (state->flags & SS_PWR_AUTO)
425 reg |= I365_PWR_AUTO;
426 if (state->flags & SS_OUTPUT_ENA)
428 if (state->Vpp != 0) {
429 if (state->Vpp == 120) {
430 reg |= I365_VPP1_12V;
431 puts (" 12V card found: ");
432 } else if (state->Vpp == state->Vcc) {
435 puts (" power not found: ");
439 if (state->Vcc != 0) {
441 if (state->Vcc == 33) {
442 puts (" 3.3V card found: ");
443 i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
444 } else if (state->Vcc == 50) {
445 puts (" 5V card found: ");
446 i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
448 puts (" power not found: ");
453 if (reg != i365_get (s, I365_POWER)) {
454 reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
455 i365_set (s, I365_POWER, reg);
458 #else /* ! CONFIG_CPC45 */
460 /* restart card voltage detection if it seems appropriate */
461 if ((state->Vcc == 0) && (state->Vpp == 0) &&
462 !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
463 cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
464 switch (state->Vcc) {
477 switch (state->Vpp) {
487 reg |= CB_SC_VPP_12V;
492 if (reg != cb_readl (s, CB_SOCKET_CONTROL))
493 cb_writel (s, CB_SOCKET_CONTROL, reg);
494 #endif /* CONFIG_CPC45 */
498 /*======================================================================
500 Generic routines to get and set controller options
502 ======================================================================*/
504 static void get_bridge_state (socket_info_t * s)
507 cirrus_get_state (s);
509 ti113x_get_state (s);
514 static void set_bridge_state (socket_info_t * s)
517 i365_set (s, I365_GBLCTL, 0x00);
518 i365_set (s, I365_GENCTL, 0x00);
520 cirrus_set_state (s);
522 ti113x_set_state (s);
526 static void set_bridge_opts (socket_info_t * s)
536 /*====================================================================*/
537 #define PD67_EXT_INDEX 0x2e /* Extension index */
538 #define PD67_EXT_DATA 0x2f /* Extension data */
539 #define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
541 #define pd67_ext_get(s, r) \
542 (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
544 static int i365_get_status (socket_info_t * s, u_int * value)
549 u_char power, vcc, vpp;
553 status = i365_get (s, I365_IDENT);
554 status = i365_get (s, I365_STATUS);
555 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
556 if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
557 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
559 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
560 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
562 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
563 *value |= (status & I365_CS_READY) ? SS_READY : 0;
564 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
567 /* Check for Cirrus CL-PD67xx chips */
568 i365_set (s, PD67_CHIP_INFO, 0);
569 val = i365_get (s, PD67_CHIP_INFO);
571 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
572 val = i365_get (s, PD67_CHIP_INFO);
573 if ((val & PD67_INFO_CHIP_ID) == 0) {
574 s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
575 i365_set (s, PD67_EXT_INDEX, 0xe5);
576 if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
577 s->type = IS_VT83C469;
580 printf ("no Cirrus Chip found\n");
585 power = i365_get (s, I365_POWER);
586 state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
587 state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
588 vcc = power & I365_VCC_MASK;
589 vpp = power & I365_VPP1_MASK;
590 state.Vcc = state.Vpp = 0;
591 if((vcc== 0) || (vpp == 0)) {
593 * On the Cirrus we get the info which card voltage
594 * we have in EXTERN DATA and write it to MISC_CTL1
596 powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
597 if (powerstate & PD67_EXD_VS1(0)) {
599 i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
602 i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
604 i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
605 power = i365_get (s, I365_POWER);
607 if (power & I365_VCC_5V) {
608 state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
611 if (power == I365_VPP1_12V)
614 /* IO card, RESET flags, IO interrupt */
615 power = i365_get (s, I365_INTCTL);
616 state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
617 if (power & I365_PC_IOCARD)
618 state.flags |= SS_IOCARD;
619 state.io_irq = power & I365_IRQ_MASK;
621 /* Card status change mask */
622 power = i365_get (s, I365_CSCINT);
623 state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
624 if (state.flags & SS_IOCARD)
625 state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
627 state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
628 state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
629 state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
631 debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
632 "io_irq %d, csc_mask %#2.2x\n", state.flags,
633 state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
635 #else /* !CONFIG_CPC45 */
637 status = cb_readl (s, CB_SOCKET_STATE);
638 *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
639 *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
640 *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
641 *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
642 /* For now, ignore cards with unsupported voltage keys */
643 if (*value & SS_XVCARD)
644 *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
645 #endif /* CONFIG_CPC45 */
647 } /* i365_get_status */
649 static int i365_set_socket (socket_info_t * s, socket_state_t * state)
653 set_bridge_state (s);
655 /* IO card, RESET flag */
657 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
658 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
659 i365_set (s, I365_INTCTL, reg);
662 cb_set_power (s, state);
665 /* Card status change interrupt mask */
666 reg = s->cs_irq << 4;
667 if (state->csc_mask & SS_DETECT)
668 reg |= I365_CSC_DETECT;
669 if (state->flags & SS_IOCARD) {
670 if (state->csc_mask & SS_STSCHG)
671 reg |= I365_CSC_STSCHG;
673 if (state->csc_mask & SS_BATDEAD)
674 reg |= I365_CSC_BVD1;
675 if (state->csc_mask & SS_BATWARN)
676 reg |= I365_CSC_BVD2;
677 if (state->csc_mask & SS_READY)
678 reg |= I365_CSC_READY;
680 i365_set (s, I365_CSCINT, reg);
681 i365_get (s, I365_CSC);
684 #else /* !CONFIG_CPC45 */
686 reg = I365_PWR_NORESET;
687 if (state->flags & SS_PWR_AUTO)
688 reg |= I365_PWR_AUTO;
689 if (state->flags & SS_OUTPUT_ENA)
692 cb_set_power (s, state);
693 reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
695 if (reg != i365_get (s, I365_POWER))
696 i365_set (s, I365_POWER, reg);
697 #endif /* CONFIG_CPC45 */
700 } /* i365_set_socket */
702 /*====================================================================*/
704 static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
709 debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
710 mem->map, mem->flags, mem->speed,
711 mem->sys_start, mem->sys_stop, mem->card_start);
715 (mem->card_start > 0x3ffffff) ||
716 (mem->sys_start > mem->sys_stop) ||
717 (mem->speed > 1000)) {
721 /* Turn off the window before changing anything */
722 if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
723 i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
725 /* Take care of high byte, for PCI controllers */
726 i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
728 base = I365_MEM (map);
729 i = (mem->sys_start >> 12) & 0x0fff;
730 if (mem->flags & MAP_16BIT)
732 if (mem->flags & MAP_0WS)
734 i365_set_pair (s, base + I365_W_START, i);
736 i = (mem->sys_stop >> 12) & 0x0fff;
737 switch (mem->speed / CYCLE_TIME) {
747 i |= I365_MEM_WS1 | I365_MEM_WS0;
750 i365_set_pair (s, base + I365_W_STOP, i);
755 i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
757 if (mem->flags & MAP_WRPROT)
758 i |= I365_MEM_WRPROT;
759 if (mem->flags & MAP_ATTRIB)
761 i365_set_pair (s, base + I365_W_OFF, i);
764 /* set System Memory map Upper Adress */
765 i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
766 i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
769 /* Turn on the window if necessary */
770 if (mem->flags & MAP_ACTIVE)
771 i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
773 } /* i365_set_mem_map */
775 static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
780 /* comment out: comparison is always false due to limited range of data type */
781 if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
782 (io->stop < io->start))
784 /* Turn off the window before changing anything */
785 if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
786 i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
787 i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
788 i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
789 ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
791 ioctl |= I365_IOCTL_WAIT (map);
792 if (io->flags & MAP_0WS)
793 ioctl |= I365_IOCTL_0WS (map);
794 if (io->flags & MAP_16BIT)
795 ioctl |= I365_IOCTL_16BIT (map);
796 if (io->flags & MAP_AUTOSZ)
797 ioctl |= I365_IOCTL_IOCS16 (map);
798 i365_set (s, I365_IOCTL, ioctl);
799 /* Turn on the window if necessary */
800 if (io->flags & MAP_ACTIVE)
801 i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
803 } /* i365_set_io_map */
805 /*====================================================================*/
807 int i82365_init (void)
813 if (SPD67290Init () != 0)
816 if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
817 /* Controller not found */
820 debug ("i82365 Device Found!\n");
822 pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
823 socket.cb_phys &= ~0xf;
826 /* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */
827 socket.cb_phys += 0xfe000000;
830 get_bridge_state (&socket);
831 set_bridge_opts (&socket);
833 i = i365_get_status (&socket, &val);
837 puts (pcic[socket.type].name);
839 printf ("i82365: Controller not found.\n");
842 if((val & SS_DETECT) != SS_DETECT){
846 #else /* !CONFIG_CPC45 */
847 if (val & SS_DETECT) {
848 if (val & SS_3VCARD) {
849 state.Vcc = state.Vpp = 33;
850 puts (" 3.3V card found: ");
851 } else if (!(val & SS_XVCARD)) {
852 state.Vcc = state.Vpp = 50;
853 puts (" 5.0V card found: ");
855 puts ("i82365: unsupported voltage key\n");
856 state.Vcc = state.Vpp = 0;
859 /* No card inserted */
863 #endif /* CONFIG_CPC45 */
866 state.flags |= SS_OUTPUT_ENA;
868 state.flags = SS_IOCARD | SS_OUTPUT_ENA;
873 i365_set_socket (&socket, &state);
875 for (i = 500; i; i--) {
876 if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
882 /* PC Card not ready for data transfer */
883 puts ("i82365 PC Card not ready for data transfer\n");
886 debug (" PC Card ready for data transfer: ");
889 mem.flags = MAP_ATTRIB | MAP_ACTIVE;
891 mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
892 mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
894 i365_set_mem_map (&socket, &mem);
898 mem.flags = MAP_ACTIVE;
900 mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE;
901 mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1;
903 i365_set_mem_map (&socket, &mem);
905 #else /* !CONFIG_CPC45 */
908 io.flags = MAP_AUTOSZ | MAP_ACTIVE;
912 i365_set_io_map (&socket, &io);
914 #endif /* CONFIG_CPC45 */
917 i82365_dump_regions (socket.dev);
923 void i82365_exit (void)
931 i365_set_io_map (&socket, &io);
937 mem.sys_stop = 0x1000;
940 i365_set_mem_map (&socket, &mem);
947 mem.sys_stop = 0x1000;
950 i365_set_mem_map (&socket, &mem);
951 #else /* !CONFIG_CPC45 */
952 socket.state.sysctl &= 0xFFFF00FF;
954 state.Vcc = state.Vpp = 0;
956 i365_set_socket (&socket, &state);
959 /*======================================================================
963 ======================================================================*/
966 static void i82365_dump_regions (pci_dev_t dev)
969 u_int *mem = (void *) socket.cb_phys;
970 u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
971 u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
973 pci_read_config_dword (dev, 0x00, tmp + 0);
974 pci_read_config_dword (dev, 0x80, tmp + 1);
976 printf ("PCI CONF: %08X ... %08X\n",
978 printf ("PCI MEM: ... %08X ... %08X\n",
979 mem[0x8 / 4], mem[0x800 / 4]);
980 printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
981 cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
982 cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
983 printf ("CIS CONF: %02X %02X %02X ...\n",
984 cis[0x200], cis[0x202], cis[0x204]);
985 printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
986 ide[0], ide[1], ide[2], ide[3],
987 ide[4], ide[5], ide[6], ide[7]);