2 * arch/ppc/kernel/pci_auto.c
4 * PCI autoconfiguration library
6 * Author: Matt Porter <mporter@mvista.com>
8 * Copyright 2000 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
24 #define DEBUGF(x...) printf(x)
29 #define PCIAUTO_IDE_MODE_MASK 0x05
35 void pciauto_region_init(struct pci_region* res)
37 res->bus_lower = res->bus_start;
40 void pciauto_region_align(struct pci_region *res, unsigned long size)
42 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
45 int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
51 DEBUGF("No resource");
55 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
57 if (addr - res->bus_start + size > res->size)
59 DEBUGF("No room in resource");
63 res->bus_lower = addr + size;
65 DEBUGF("address=0x%lx", addr);
79 void pciauto_setup_device(struct pci_controller *hose,
80 pci_dev_t dev, int bars_num,
81 struct pci_region *mem,
82 struct pci_region *io)
84 unsigned int bar_value, bar_response, bar_size;
85 unsigned int cmdstat = 0;
86 struct pci_region *bar_res;
90 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
91 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
93 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4)
95 /* Tickle the BAR and get the response */
96 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
97 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
99 /* If BAR is not implemented go to the next BAR */
105 /* Check the BAR type and set our address mask */
106 if (bar_response & PCI_BASE_ADDRESS_SPACE)
108 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
111 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
115 if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
116 PCI_BASE_ADDRESS_MEM_TYPE_64)
119 bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
122 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
125 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0)
127 /* Write it out and update our limit */
128 pci_hose_write_config_dword(hose, dev, bar, bar_value);
131 * If we are a 64-bit decoder then increment to the
132 * upper 32 bits of the bar and force it to locate
133 * in the lower 4GB of memory.
138 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
141 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
142 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
150 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
151 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
152 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
155 static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
156 pci_dev_t dev, int sub_bus)
158 struct pci_region *pci_mem = hose->pci_mem;
159 struct pci_region *pci_io = hose->pci_io;
160 unsigned int cmdstat;
162 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
164 /* Configure bus number registers */
165 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
166 /* TBS: passed in sub_bus is correct, removed the +1 */
167 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
168 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
172 /* Round memory allocator to 1MB boundary */
173 pciauto_region_align(pci_mem, 0x100000);
175 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
176 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
177 (pci_mem->bus_lower & 0xfff00000) >> 16);
179 cmdstat |= PCI_COMMAND_MEMORY;
184 /* Round I/O allocator to 4KB boundary */
185 pciauto_region_align(pci_io, 0x1000);
187 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
188 (pci_io->bus_lower & 0x0000f000) >> 8);
189 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
190 (pci_io->bus_lower & 0xffff0000) >> 16);
192 cmdstat |= PCI_COMMAND_IO;
195 /* We don't support prefetchable memory for now, so disable */
196 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
197 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
199 /* Enable memory and I/O accesses, enable bus master */
200 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
203 static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
204 pci_dev_t dev, int sub_bus)
206 struct pci_region *pci_mem = hose->pci_mem;
207 struct pci_region *pci_io = hose->pci_io;
209 /* Configure bus number registers */
210 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
214 /* Round memory allocator to 1MB boundary */
215 pciauto_region_align(pci_mem, 0x100000);
217 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
218 (pci_mem->bus_lower-1) >> 16);
223 /* Round I/O allocator to 4KB boundary */
224 pciauto_region_align(pci_io, 0x1000);
226 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
227 ((pci_io->bus_lower-1) & 0x0000f000) >> 8);
228 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
229 ((pci_io->bus_lower-1) & 0xffff0000) >> 16);
237 void pciauto_config_init(struct pci_controller *hose)
241 hose->pci_io = hose->pci_mem = NULL;
243 for (i=0; i<hose->region_count; i++)
245 switch(hose->regions[i].flags)
249 hose->pci_io->size < hose->regions[i].size)
250 hose->pci_io = hose->regions + i;
253 if (!hose->pci_mem ||
254 hose->pci_mem->size < hose->regions[i].size)
255 hose->pci_mem = hose->regions + i;
263 pciauto_region_init(hose->pci_mem);
265 DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
266 hose->pci_mem->bus_start,
267 hose->pci_mem->bus_start + hose->pci_mem->size - 1);
272 pciauto_region_init(hose->pci_io);
274 DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
275 hose->pci_io->bus_start,
276 hose->pci_io->bus_start + hose->pci_io->size - 1);
280 /* HJF: Changed this to return int. I think this is required
281 * to get the correct result when scanning bridges
283 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
285 unsigned int sub_bus = PCI_BUS(dev);
286 unsigned short class;
287 unsigned char prg_iface;
290 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
294 case PCI_CLASS_BRIDGE_PCI:
295 hose->current_busno++;
296 pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
298 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
300 /* TBS: Passing in current_busno allows for sibling P2P bridges */
301 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
303 * TBS: need to figure out if this is a subordinate bridge on the bus
304 * to be able to properly set the pri/sec/sub bridge registers.
306 n = pci_hose_scan_bus(hose, hose->current_busno);
308 /* TBS: figure out the deepest we've gone for this leg */
309 sub_bus = max(n, sub_bus);
310 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
312 sub_bus = hose->current_busno;
315 case PCI_CLASS_STORAGE_IDE:
316 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
317 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK))
319 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
323 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
326 case PCI_CLASS_BRIDGE_CARDBUS:
327 /* just do a minimal setup of the bridge, let the OS take care of the rest */
328 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
330 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
333 hose->current_busno++;
336 #ifdef CONFIG_MPC5200
337 case PCI_CLASS_BRIDGE_OTHER:
338 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
344 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
351 #endif /* CONFIG_PCI */