1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip PCIe PHY driver
5 * Copyright (c) 2016 Rockchip, Inc.
6 * Copyright (c) 2020 Amarula Solutions(India)
12 #include <dm/device_compat.h>
17 #include <linux/iopoll.h>
18 #include <asm/arch-rockchip/clock.h>
20 #include "pcie_rockchip.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data)
28 reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
29 reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
30 writel(reg, phy->reg_base + PCIE_PHY_CONF);
34 reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE,
37 writel(reg, phy->reg_base + PCIE_PHY_CONF);
41 reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE,
44 writel(reg, phy->reg_base + PCIE_PHY_CONF);
47 static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy)
52 ret = reset_deassert(&phy->phy_rst);
54 dev_err(dev, "failed to assert phy reset\n");
58 reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
61 writel(reg, phy->reg_base + PCIE_PHY_CONF);
63 reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF,
65 PHY_LANE_IDLE_A_SHIFT);
66 writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
69 ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
71 status & PHY_PLL_LOCKED,
75 dev_err(&phy->dev, "pll lock timeout!\n");
79 phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
80 phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
83 ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
85 !(status & PHY_PLL_OUTPUT),
89 dev_err(&phy->dev, "pll output enable timeout!\n");
93 reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
96 writel(reg, phy->reg_base + PCIE_PHY_CONF);
99 ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
101 status & PHY_PLL_LOCKED,
105 dev_err(&phy->dev, "pll relock timeout!\n");
112 reset_assert(&phy->phy_rst);
116 static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy)
121 reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF,
123 PHY_LANE_IDLE_A_SHIFT);
124 writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
126 ret = reset_assert(&phy->phy_rst);
128 dev_err(dev, "failed to assert phy reset\n");
135 static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy)
139 ret = clk_enable(&phy->refclk);
141 dev_err(dev, "failed to enable refclk clock\n");
145 ret = reset_assert(&phy->phy_rst);
147 dev_err(dev, "failed to assert phy reset\n");
154 clk_disable(&phy->refclk);
158 static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy)
160 clk_disable(&phy->refclk);
165 static struct rockchip_pcie_phy_ops pcie_phy_ops = {
166 .init = rockchip_pcie_phy_init,
167 .power_on = rockchip_pcie_phy_power_on,
168 .power_off = rockchip_pcie_phy_power_off,
169 .exit = rockchip_pcie_phy_exit,
172 int rockchip_pcie_phy_get(struct udevice *dev)
174 struct rockchip_pcie *priv = dev_get_priv(dev);
175 struct rockchip_pcie_phy *phy_priv = &priv->rk_phy;
180 phandle = dev_read_u32_default(dev, "phys", 0);
181 phy_node = ofnode_get_by_phandle(phandle);
182 if (!ofnode_valid(phy_node)) {
183 dev_err(dev, "failed to found pcie-phy\n");
187 phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
189 ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk);
191 dev_err(dev, "failed to get refclk clock phandle\n");
195 ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst);
197 dev_err(dev, "failed to get phy reset phandle\n");
201 phy_priv->ops = &pcie_phy_ops;
202 priv->phy = phy_priv;