1 // SPDX-License-Identifier: GPL-2.0
3 * Phytium PCIE host driver
5 * Heavily based on drivers/pci/pcie_xilinx.c
16 * struct phytium_pcie - phytium PCIe controller state
17 * @cfg_base: The base address of memory mapped configuration space
24 * phytium_pci_skip_dev()
25 * @parent: Identifies the PCIe device to access
27 * Checks whether the parent of the PCIe device is bridge
29 * Return: true if it is bridge, else false.
31 static int phytium_pci_skip_dev(pci_dev_t parent)
33 unsigned char pos, id;
34 unsigned long addr = 0x40000000;
35 unsigned short capreg;
36 unsigned char port_type;
38 addr += PCI_BUS(parent) << 20;
39 addr += PCI_DEV(parent) << 15;
40 addr += PCI_FUNC(parent) << 12;
44 pos = readb(addr + pos);
48 id = readb(addr + pos);
52 capreg = readw(addr + pos + 2);
53 port_type = (capreg >> 4) & 0xf;
54 if (port_type == 0x6 || port_type == 0x4)
65 * pci_phytium_conf_address() - Calculate the address of a config access
66 * @bus: Pointer to the PCI bus
67 * @bdf: Identifies the PCIe device to access
68 * @offset: The offset into the device's configuration space
69 * @paddress: Pointer to the pointer to write the calculates address to
71 * Calculates the address that should be accessed to perform a PCIe
72 * configuration space access for a given device identified by the PCIe
73 * controller device @pcie and the bus, device & function numbers in @bdf. If
74 * access to the device is not valid then the function will return an error
75 * code. Otherwise the address to access will be written to the pointer pointed
78 static int pci_phytium_conf_address(struct udevice *bus, pci_dev_t bdf,
82 struct phytium_pcie *pcie = dev_get_priv(bus);
86 unsigned int bus_no = PCI_BUS(bdf);
87 unsigned int dev_no = PCI_DEV(bdf);
89 bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
91 addr = pcie->cfg_base;
92 addr += PCI_BUS(bdf) << 20;
93 addr += PCI_DEV(bdf) << 15;
94 addr += PCI_FUNC(bdf) << 12;
96 if (bus_no > 0 && dev_no > 0) {
97 if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
98 PCI_HEADER_TYPE_BRIDGE)
100 if (phytium_pci_skip_dev(bdf_parent))
111 * pci_phytium_read_config() - Read from configuration space
112 * @bus: Pointer to the PCI bus
113 * @bdf: Identifies the PCIe device to access
114 * @offset: The offset into the device's configuration space
115 * @valuep: A pointer at which to store the read value
116 * @size: Indicates the size of access to perform
118 * Read a value of size @size from offset @offset within the configuration
119 * space of the device identified by the bus, device & function numbers in @bdf
120 * on the PCI bus @bus.
122 static int pci_phytium_read_config(struct udevice *bus, pci_dev_t bdf,
123 uint offset, ulong *valuep,
124 enum pci_size_t size)
126 return pci_generic_mmap_read_config(bus, pci_phytium_conf_address,
127 bdf, offset, valuep, size);
131 * pci_phytium_write_config() - Write to configuration space
132 * @bus: Pointer to the PCI bus
133 * @bdf: Identifies the PCIe device to access
134 * @offset: The offset into the device's configuration space
135 * @value: The value to write
136 * @size: Indicates the size of access to perform
138 * Write the value @value of size @size from offset @offset within the
139 * configuration space of the device identified by the bus, device & function
140 * numbers in @bdf on the PCI bus @bus.
142 static int pci_phytium_write_config(struct udevice *bus, pci_dev_t bdf,
143 uint offset, ulong value,
144 enum pci_size_t size)
146 return pci_generic_mmap_write_config(bus, pci_phytium_conf_address,
147 bdf, offset, value, size);
151 * pci_phytium_ofdata_to_platdata() - Translate from DT to device state
152 * @dev: A pointer to the device being operated on
154 * Translate relevant data from the device tree pertaining to device @dev into
155 * state that the driver will later make use of. This state is stored in the
156 * device's private data structure.
158 * Return: 0 on success, else -EINVAL
160 static int pci_phytium_ofdata_to_platdata(struct udevice *dev)
162 struct phytium_pcie *pcie = dev_get_priv(dev);
163 struct fdt_resource reg_res;
165 DECLARE_GLOBAL_DATA_PTR;
169 err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
172 pr_err("\"reg\" resource not found\n");
176 pcie->cfg_base = map_physmem(reg_res.start,
177 fdt_resource_size(®_res),
183 static const struct dm_pci_ops pci_phytium_ops = {
184 .read_config = pci_phytium_read_config,
185 .write_config = pci_phytium_write_config,
188 static const struct udevice_id pci_phytium_ids[] = {
189 { .compatible = "phytium,pcie-host-1.0" },
193 U_BOOT_DRIVER(pci_phytium) = {
194 .name = "pci_phytium",
196 .of_match = pci_phytium_ids,
197 .ops = &pci_phytium_ops,
198 .ofdata_to_platdata = pci_phytium_ofdata_to_platdata,
199 .priv_auto_alloc_size = sizeof(struct phytium_pcie),