1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
5 * Copyright (c) 2017-2019 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
13 #include <generic-phy.h>
18 #include <dm/devres.h>
19 #include <linux/iopoll.h>
20 #include <linux/list.h>
22 /* PCIe shared registers */
23 #define PCIE_SYS_CFG 0x00
24 #define PCIE_INT_ENABLE 0x0c
25 #define PCIE_CFG_ADDR 0x20
26 #define PCIE_CFG_DATA 0x24
28 /* PCIe per port registers */
29 #define PCIE_BAR0_SETUP 0x10
30 #define PCIE_CLASS 0x34
31 #define PCIE_LINK_STATUS 0x50
33 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
34 #define PCIE_PORT_PERST(x) BIT(1 + (x))
35 #define PCIE_PORT_LINKUP BIT(0)
36 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
38 #define PCIE_BAR_ENABLE BIT(0)
39 #define PCIE_REVISION_ID BIT(0)
40 #define PCIE_CLASS_CODE (0x60400 << 8)
41 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
42 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
43 #define PCIE_CONF_ADDR(regn, bdf) \
44 (PCIE_CONF_REG(regn) | (bdf))
46 /* MediaTek specific configuration registers */
47 #define PCIE_FTS_NUM 0x70c
48 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
49 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
51 #define PCIE_FC_CREDIT 0x73c
52 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
53 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
55 struct mtk_pcie_port {
57 struct list_head list;
58 struct mtk_pcie *pcie;
59 struct reset_ctl reset;
68 struct list_head ports;
71 static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf,
72 uint offset, void **paddress)
74 struct mtk_pcie *pcie = dev_get_priv(udev);
76 writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
77 *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
82 static int mtk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
83 uint offset, ulong *valuep,
86 return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
87 bdf, offset, valuep, size);
90 static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
91 uint offset, ulong value,
94 return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
95 bdf, offset, value, size);
98 static const struct dm_pci_ops mtk_pcie_ops = {
99 .read_config = mtk_pcie_read_config,
100 .write_config = mtk_pcie_write_config,
103 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
105 list_del(&port->list);
109 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
111 struct mtk_pcie *pcie = port->pcie;
112 u32 slot = PCI_DEV(port->slot << 11);
116 /* assert port PERST_N */
117 setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
118 /* de-assert port PERST_N */
119 clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
121 /* 100ms timeout value should be enough for Gen1/2 training */
122 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
123 !!(val & PCIE_PORT_LINKUP), 100000);
127 /* disable interrupt */
128 clrbits_le32(pcie->base + PCIE_INT_ENABLE,
129 PCIE_PORT_INT_EN(port->slot));
131 /* map to all DDR region. We need to set it before cfg operation. */
132 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
133 port->base + PCIE_BAR0_SETUP);
135 /* configure class code and revision ID */
136 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
138 /* configure FC credit */
139 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
140 pcie->base + PCIE_CFG_ADDR);
141 clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
142 PCIE_FC_CREDIT_VAL(0x806c));
144 /* configure RC FTS number to 250 when it leaves L0s */
145 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
146 clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
147 PCIE_FTS_NUM_L0(0x50));
152 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
156 err = clk_enable(&port->sys_ck);
160 err = reset_assert(&port->reset);
164 err = reset_deassert(&port->reset);
168 err = generic_phy_init(&port->phy);
172 err = generic_phy_power_on(&port->phy);
176 if (!mtk_pcie_startup_port(port))
179 pr_err("Port%d link down\n", port->slot);
181 mtk_pcie_port_free(port);
184 static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
186 struct mtk_pcie *pcie = dev_get_priv(dev);
187 struct mtk_pcie_port *port;
191 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
195 snprintf(name, sizeof(name), "port%d", slot);
196 port->base = dev_remap_addr_name(dev, name);
200 snprintf(name, sizeof(name), "sys_ck%d", slot);
201 err = clk_get_by_name(dev, name, &port->sys_ck);
205 err = reset_get_by_index(dev, slot, &port->reset);
209 err = generic_phy_get_by_index(dev, slot, &port->phy);
216 INIT_LIST_HEAD(&port->list);
217 list_add_tail(&port->list, &pcie->ports);
222 static int mtk_pcie_probe(struct udevice *dev)
224 struct mtk_pcie *pcie = dev_get_priv(dev);
225 struct mtk_pcie_port *port, *tmp;
229 INIT_LIST_HEAD(&pcie->ports);
231 pcie->base = dev_remap_addr_name(dev, "subsys");
235 err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
239 /* enable top level clock */
240 err = clk_enable(&pcie->free_ck);
244 dev_for_each_subnode(subnode, dev) {
245 struct fdt_pci_addr addr;
248 if (!ofnode_is_available(subnode))
251 err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
255 slot = PCI_DEV(addr.phys_hi);
257 err = mtk_pcie_parse_port(dev, slot);
262 /* enable each port, and then check link status */
263 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
264 mtk_pcie_enable_port(port);
269 static const struct udevice_id mtk_pcie_ids[] = {
270 { .compatible = "mediatek,mt7623-pcie", },
274 U_BOOT_DRIVER(pcie_mediatek) = {
275 .name = "pcie_mediatek",
277 .of_match = mtk_pcie_ids,
278 .ops = &mtk_pcie_ops,
279 .probe = mtk_pcie_probe,
280 .priv_auto_alloc_size = sizeof(struct mtk_pcie),