drivers/pci/pcie_layerscape_gen4.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *
   5  * PCIe Gen4 driver for NXP Layerscape SoCs
   6  * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
   7  */
   8
   9 #ifndef _PCIE_LAYERSCAPE_GEN4_H_
  10 #define _PCIE_LAYERSCAPE_GEN4_H_
  11 #include <pci.h>
  12 #include <dm.h>
  13 #include <linux/bitops.h>
  14
  15 #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
  16 #define CONFIG_SYS_PCI_MEMORY_SIZE              (4 * 1024 * 1024 * 1024ULL)
  17 #endif
  18
  19 #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
  20 #define CONFIG_SYS_PCI_EP_MEMORY_BASE           CONFIG_SYS_LOAD_ADDR
  21 #endif
  22
  23 #define PCIE_PF_NUM                             2
  24 #define PCIE_VF_NUM                             32
  25
  26 #define LS_G4_PF0                               0
  27 #define LS_G4_PF1                               1
  28 #define PF_BAR_NUM                              4
  29 #define VF_BAR_NUM                              4
  30 #define PCIE_BAR_SIZE                           (8 * 1024)              /* 8K */
  31 #define PCIE_BAR0_SIZE                          PCIE_BAR_SIZE
  32 #define PCIE_BAR1_SIZE                          PCIE_BAR_SIZE
  33 #define PCIE_BAR2_SIZE                          PCIE_BAR_SIZE
  34 #define PCIE_BAR4_SIZE                          PCIE_BAR_SIZE
  35 #define SIZE_1T                                 (1024 * 1024 * 1024 * 1024ULL)
  36
  37 /* GPEX CSR */
  38 #define GPEX_CLASSCODE                          0x474
  39 #define GPEX_CLASSCODE_SHIFT                    16
  40 #define GPEX_CLASSCODE_MASK                     0xffff
  41
  42 #define GPEX_CFG_READY                          0x4b0
  43 #define PCIE_CONFIG_READY                       BIT(0)
  44
  45 #define GPEX_BAR_ENABLE                         0x4d4
  46 #define GPEX_BAR_SIZE_LDW                       0x4d8
  47 #define GPEX_BAR_SIZE_UDW                       0x4dC
  48 #define GPEX_BAR_SELECT                         0x4e0
  49
  50 #define BAR_POS(bar, pf, vf_bar)                \
  51         ((bar) + (pf) * PF_BAR_NUM + (vf_bar) * PCIE_PF_NUM * PF_BAR_NUM)
  52
  53 #define GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf)        (0x644 + (pf) * 4)
  54 #define TTL_VF_MASK                             0xffff
  55 #define TTL_VF_SHIFT                            16
  56 #define INI_VF_MASK                             0xffff
  57 #define INI_VF_SHIFT                            0
  58 #define GPEX_SRIOV_VF_OFFSET_STRIDE(pf)         (0x704 + (pf) * 4)
  59
  60 /* PAB CSR */
  61 #define PAB_CTRL                                0x808
  62 #define PAB_CTRL_APIO_EN                        BIT(0)
  63 #define PAB_CTRL_PPIO_EN                        BIT(1)
  64 #define PAB_CTRL_MAX_BRST_LEN_SHIFT             4
  65 #define PAB_CTRL_MAX_BRST_LEN_MASK              0x3
  66 #define PAB_CTRL_PAGE_SEL_SHIFT                 13
  67 #define PAB_CTRL_PAGE_SEL_MASK                  0x3f
  68 #define PAB_CTRL_FUNC_SEL_SHIFT                 19
  69 #define PAB_CTRL_FUNC_SEL_MASK                  0x1ff
  70
  71 #define PAB_RST_CTRL                            0x820
  72 #define PAB_BR_STAT                             0x80c
  73
  74 /* AXI PIO Engines */
  75 #define PAB_AXI_PIO_CTRL(idx)                   (0x840 + 0x10 * (idx))
  76 #define APIO_EN                                 BIT(0)
  77 #define MEM_WIN_EN                              BIT(1)
  78 #define IO_WIN_EN                               BIT(2)
  79 #define CFG_WIN_EN                              BIT(3)
  80 #define PAB_AXI_PIO_STAT(idx)                   (0x844 + 0x10 * (idx))
  81 #define PAB_AXI_PIO_SL_CMD_STAT(idx)            (0x848 + 0x10 * (idx))
  82 #define PAB_AXI_PIO_SL_ADDR_STAT(idx)           (0x84c + 0x10 * (idx))
  83 #define PAB_AXI_PIO_SL_EXT_ADDR_STAT(idx)       (0xb8a0 + 0x4 * (idx))
  84
  85 /* PEX PIO Engines */
  86 #define PAB_PEX_PIO_CTRL(idx)                   (0x8c0 + 0x10 * (idx))
  87 #define PPIO_EN                                 BIT(0)
  88 #define PAB_PEX_PIO_STAT(idx)                   (0x8c4 + 0x10 * (idx))
  89 #define PAB_PEX_PIO_MT_STAT(idx)                (0x8c8 + 0x10 * (idx))
  90
  91 #define INDIRECT_ADDR_BNDRY                     0xc00
  92 #define PAGE_IDX_SHIFT                          10
  93 #define PAGE_ADDR_MASK                          0x3ff
  94
  95 #define OFFSET_TO_PAGE_IDX(off)                 \
  96         (((off) >> PAGE_IDX_SHIFT) & PAB_CTRL_PAGE_SEL_MASK)
  97
  98 #define OFFSET_TO_PAGE_ADDR(off)                \
  99         (((off) & PAGE_ADDR_MASK) | INDIRECT_ADDR_BNDRY)
 100
 101 /* APIO WINs */
 102 #define PAB_AXI_AMAP_CTRL(idx)                  (0xba0 + 0x10 * (idx))
 103 #define PAB_EXT_AXI_AMAP_SIZE(idx)              (0xbaf0 + 0x4 * (idx))
 104 #define PAB_AXI_AMAP_AXI_WIN(idx)               (0xba4 + 0x10 * (idx))
 105 #define PAB_EXT_AXI_AMAP_AXI_WIN(idx)           (0x80a0 + 0x4 * (idx))
 106 #define PAB_AXI_AMAP_PEX_WIN_L(idx)             (0xba8 + 0x10 * (idx))
 107 #define PAB_AXI_AMAP_PEX_WIN_H(idx)             (0xbac + 0x10 * (idx))
 108 #define PAB_AXI_AMAP_PCI_HDR_PARAM(idx)         (0x5ba0 + 0x4 * (idx))
 109 #define FUNC_NUM_PCIE_MASK                      GENMASK(7, 0)
 110
 111 #define AXI_AMAP_CTRL_EN                        BIT(0)
 112 #define AXI_AMAP_CTRL_TYPE_SHIFT                1
 113 #define AXI_AMAP_CTRL_TYPE_MASK                 0x3
 114 #define AXI_AMAP_CTRL_SIZE_SHIFT                10
 115 #define AXI_AMAP_CTRL_SIZE_MASK                 0x3fffff
 116
 117 #define PAB_TARGET_BUS(x)                       (((x) & 0xff) << 24)
 118 #define PAB_TARGET_DEV(x)                       (((x) & 0x1f) << 19)
 119 #define PAB_TARGET_FUNC(x)                      (((x) & 0x7) << 16)
 120
 121 #define PAB_AXI_TYPE_CFG                        0x00
 122 #define PAB_AXI_TYPE_IO                         0x01
 123 #define PAB_AXI_TYPE_MEM                        0x02
 124 #define PAB_AXI_TYPE_ATOM                       0x03
 125
 126 #define PAB_WINS_NUM                            256
 127
 128 /* PPIO WINs RC mode */
 129 #define PAB_PEX_AMAP_CTRL(idx)                  (0x4ba0 + 0x10 * (idx))
 130 #define PAB_EXT_PEX_AMAP_SIZE(idx)              (0xbef0 + 0x04 * (idx))
 131 #define PAB_PEX_AMAP_AXI_WIN(idx)               (0x4ba4 + 0x10 * (idx))
 132 #define PAB_EXT_PEX_AMAP_AXI_WIN(idx)           (0xb4a0 + 0x04 * (idx))
 133 #define PAB_PEX_AMAP_PEX_WIN_L(idx)             (0x4ba8 + 0x10 * (idx))
 134 #define PAB_PEX_AMAP_PEX_WIN_H(idx)             (0x4bac + 0x10 * (idx))
 135
 136 #define IB_TYPE_MEM_F                           0x2
 137 #define IB_TYPE_MEM_NF                          0x3
 138
 139 #define PEX_AMAP_CTRL_TYPE_SHIFT                0x1
 140 #define PEX_AMAP_CTRL_EN_SHIFT                  0x0
 141 #define PEX_AMAP_CTRL_TYPE_MASK                 0x3
 142 #define PEX_AMAP_CTRL_EN_MASK                   0x1
 143
 144 /* PPIO WINs EP mode */
 145 #define PAB_PEX_BAR_AMAP(pf, bar)               \
 146         (0x1ba0 + 0x20 * (pf) + 4 * (bar))
 147 #define BAR_AMAP_EN                             BIT(0)
 148 #define PAB_EXT_PEX_BAR_AMAP(pf, bar)           \
 149         (0x84a0 + 0x20 * (pf) + 4 * (bar))
 150
 151 /* CCSR registers */
 152 #define PCIE_LINK_CTRL_STA                      0x5c
 153 #define PCIE_LINK_SPEED_SHIFT                   16
 154 #define PCIE_LINK_SPEED_MASK                    0x0f
 155 #define PCIE_LINK_WIDTH_SHIFT                   20
 156 #define PCIE_LINK_WIDTH_MASK                    0x3f
 157 #define PCIE_SRIOV_CAPABILITY                   0x2a0
 158 #define PCIE_SRIOV_VF_OFFSET_STRIDE             0x2b4
 159
 160 /* LUT registers */
 161 #define PCIE_LUT_UDR(n)                         (0x800 + (n) * 8)
 162 #define PCIE_LUT_LDR(n)                         (0x804 + (n) * 8)
 163 #define PCIE_LUT_ENABLE                         BIT(31)
 164 #define PCIE_LUT_ENTRY_COUNT                    32
 165
 166 /* PF control registers */
 167 #define PCIE_LTSSM_STA                          0x7fc
 168 #define LTSSM_STATE_MASK                        0x7f
 169 #define LTSSM_PCIE_L0                           0x2d /* L0 state */
 170
 171 #define PCIE_SRDS_PRTCL(idx)                    (PCIE1 + (idx))
 172 #define PCIE_SYS_BASE_ADDR                      0x3400000
 173 #define PCIE_CCSR_SIZE                          0x0100000
 174
 175 struct ls_pcie_g4 {
 176         int idx;
 177         struct list_head list;
 178         struct udevice *bus;
 179         struct fdt_resource ccsr_res;
 180         struct fdt_resource cfg_res;
 181         struct fdt_resource lut_res;
 182         struct fdt_resource pf_ctrl_res;
 183         void __iomem *ccsr;
 184         void __iomem *cfg;
 185         void __iomem *lut;
 186         void __iomem *pf_ctrl;
 187         bool big_endian;
 188         bool enabled;
 189         int next_lut_index;
 190         struct pci_controller hose;
 191         int stream_id_cur;
 192         int mode;
 193         int sriov_support;
 194 };
 195
 196 extern struct list_head ls_pcie_g4_list;
 197
 198 static inline void lut_writel(struct ls_pcie_g4 *pcie, unsigned int value,
 199                               unsigned int offset)
 200 {
 201         if (pcie->big_endian)
 202                 out_be32(pcie->lut + offset, value);
 203         else
 204                 out_le32(pcie->lut + offset, value);
 205 }
 206
 207 static inline u32 lut_readl(struct ls_pcie_g4 *pcie, unsigned int offset)
 208 {
 209         if (pcie->big_endian)
 210                 return in_be32(pcie->lut + offset);
 211         else
 212                 return in_le32(pcie->lut + offset);
 213 }
 214
 215 static inline void ccsr_set_page(struct ls_pcie_g4 *pcie, u8 pg_idx)
 216 {
 217         u32 val;
 218
 219         val = in_le32(pcie->ccsr + PAB_CTRL);
 220         val &= ~(PAB_CTRL_PAGE_SEL_MASK << PAB_CTRL_PAGE_SEL_SHIFT);
 221         val |= (pg_idx & PAB_CTRL_PAGE_SEL_MASK) << PAB_CTRL_PAGE_SEL_SHIFT;
 222
 223         out_le32(pcie->ccsr + PAB_CTRL, val);
 224 }
 225
 226 static inline unsigned int ccsr_readl(struct ls_pcie_g4 *pcie, u32 offset)
 227 {
 228         if (offset < INDIRECT_ADDR_BNDRY) {
 229                 ccsr_set_page(pcie, 0);
 230                 return in_le32(pcie->ccsr + offset);
 231         }
 232
 233         ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
 234         return in_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset));
 235 }
 236
 237 static inline void ccsr_writel(struct ls_pcie_g4 *pcie, u32 offset, u32 value)
 238 {
 239         if (offset < INDIRECT_ADDR_BNDRY) {
 240                 ccsr_set_page(pcie, 0);
 241                 out_le32(pcie->ccsr + offset, value);
 242         } else {
 243                 ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
 244                 out_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset), value);
 245         }
 246 }
 247
 248 static inline unsigned int pf_ctrl_readl(struct ls_pcie_g4 *pcie, u32 offset)
 249 {
 250         if (pcie->big_endian)
 251                 return in_be32(pcie->pf_ctrl + offset);
 252         else
 253                 return in_le32(pcie->pf_ctrl + offset);
 254 }
 255
 256 static inline void pf_ctrl_writel(struct ls_pcie_g4 *pcie, u32 offset,
 257                                   u32 value)
 258 {
 259         if (pcie->big_endian)
 260                 out_be32(pcie->pf_ctrl + offset, value);
 261         else
 262                 out_le32(pcie->pf_ctrl + offset, value);
 263 }
 264
 265 #endif /* _PCIE_LAYERSCAPE_GEN4_H_ */