1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2020 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
10 #include <asm/arch/fsl_serdes.h>
13 #ifdef CONFIG_OF_BOARD_SETUP
14 #include <linux/libfdt.h>
15 #include <fdt_support.h>
17 #include <asm/arch/clock.h>
19 #include "pcie_layerscape.h"
20 #include "pcie_layerscape_fixup_common.h"
22 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
24 * Return next available LUT index.
26 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
28 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
29 return pcie->next_lut_index++;
31 return -ENOSPC; /* LUT is full */
34 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
38 out_be32(pcie->lut + offset, value);
40 out_le32(pcie->lut + offset, value);
44 * Program a single LUT entry
46 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
49 /* leave mask as all zeroes, want to match all bits */
50 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
51 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
55 * An msi-map is a property to be added to the pci controller
56 * node. It is a table, where each entry consists of 4 fields
59 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
60 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
62 static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
63 u32 devid, u32 streamid)
71 /* find pci controller node */
72 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
75 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
76 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
77 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
78 svr == SVR_LS2048A || svr == SVR_LS2044A ||
79 svr == SVR_LS2081A || svr == SVR_LS2041A)
80 compat = "fsl,ls2088a-pcie";
82 compat = CONFIG_FSL_PCIE_COMPAT;
84 nodeoffset = fdt_node_offset_by_compat_reg(blob,
85 compat, pcie->dbi_res.start);
91 /* get phandle to MSI controller */
92 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
94 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
98 phandle = fdt32_to_cpu(*prop);
100 /* set one msi-map row */
101 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
102 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
103 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
104 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
108 * An iommu-map is a property to be added to the pci controller
109 * node. It is a table, where each entry consists of 4 fields
112 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
113 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
115 static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
116 u32 devid, u32 streamid)
125 /* find pci controller node */
126 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
127 pcie->dbi_res.start);
128 if (nodeoffset < 0) {
129 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
130 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
131 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
132 svr == SVR_LS2048A || svr == SVR_LS2044A ||
133 svr == SVR_LS2081A || svr == SVR_LS2041A)
134 compat = "fsl,ls2088a-pcie";
136 compat = CONFIG_FSL_PCIE_COMPAT;
139 nodeoffset = fdt_node_offset_by_compat_reg(blob,
140 compat, pcie->dbi_res.start);
146 /* get phandle to iommu controller */
147 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
149 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
150 __func__, pcie->idx);
154 /* set iommu-map row */
155 iommu_map[0] = cpu_to_fdt32(devid);
156 iommu_map[1] = *++prop;
157 iommu_map[2] = cpu_to_fdt32(streamid);
158 iommu_map[3] = cpu_to_fdt32(1);
161 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
164 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
168 static void fdt_fixup_pcie_ls(void *blob)
170 struct udevice *dev, *bus;
171 struct ls_pcie *pcie;
176 /* Scan all known buses */
177 for (pci_find_first_device(&dev);
179 pci_find_next_device(&dev)) {
180 for (bus = dev; device_is_on_pci_bus(bus);)
182 pcie = dev_get_priv(bus);
184 streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
186 debug("ERROR: no stream ids free\n");
189 pcie->stream_id_cur++;
192 index = ls_pcie_next_lut_index(pcie);
194 debug("ERROR: no LUT indexes free\n");
198 /* the DT fixup must be relative to the hose first_busno */
199 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
200 /* map PCI b.d.f to streamID in LUT */
201 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
203 /* update msi-map in device tree */
204 fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
206 /* update iommu-map in device tree */
207 fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
210 pcie_board_fix_fdt(blob);
214 static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
220 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
221 pcie->dbi_res.start);
223 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
224 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
225 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
226 svr == SVR_LS2048A || svr == SVR_LS2044A ||
227 svr == SVR_LS2081A || svr == SVR_LS2041A)
228 compat = "fsl,ls2088a-pcie";
230 compat = CONFIG_FSL_PCIE_COMPAT;
232 off = fdt_node_offset_by_compat_reg(blob,
233 compat, pcie->dbi_res.start);
239 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
240 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
242 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
245 static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
249 off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
250 pcie->dbi_res.start);
254 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
255 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
257 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
260 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
262 ft_pcie_ep_fix(blob, pcie);
263 ft_pcie_rc_fix(blob, pcie);
266 /* Fixup Kernel DT for PCIe */
267 void ft_pci_setup_ls(void *blob, bd_t *bd)
269 struct ls_pcie *pcie;
271 list_for_each_entry(pcie, &ls_pcie_list, list)
272 ft_pcie_ls_setup(blob, pcie);
274 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
275 fdt_fixup_pcie_ls(blob);
279 #else /* !CONFIG_OF_BOARD_SETUP */
280 void ft_pci_setup_ls(void *blob, bd_t *bd)