1 // SPDX-License-Identifier: GPL-2.0
3 * Intel FPGA PCIe host controller driver
5 * Copyright (C) 2013-2018 Intel Corporation. All rights reserved
13 #include <dm/device_compat.h>
15 #define RP_TX_REG0 0x2000
16 #define RP_TX_CNTRL 0x2004
17 #define RP_TX_SOP BIT(0)
18 #define RP_TX_EOP BIT(1)
19 #define RP_RXCPL_STATUS 0x200C
20 #define RP_RXCPL_SOP BIT(0)
21 #define RP_RXCPL_EOP BIT(1)
22 #define RP_RXCPL_REG 0x2008
23 #define P2A_INT_STATUS 0x3060
24 #define P2A_INT_STS_ALL 0xf
25 #define P2A_INT_ENABLE 0x3070
26 #define RP_CAP_OFFSET 0x70
28 /* TLP configuration type 0 and 1 */
29 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
30 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
31 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
32 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
33 #define TLP_PAYLOAD_SIZE 0x01
34 #define TLP_READ_TAG 0x1d
35 #define TLP_WRITE_TAG 0x10
38 #define RP_CFG_ADDR(pcie, reg) \
39 ((pcie->hip_base) + (reg) + (1 << 20))
40 #define RP_SECONDARY(pcie) \
41 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
42 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
44 #define TLP_CFGRD_DW0(pcie, bus) \
45 ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \
46 : TLP_FMTTYPE_CFGRD0) << 24) | \
49 #define TLP_CFGWR_DW0(pcie, bus) \
50 ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \
51 : TLP_FMTTYPE_CFGWR0) << 24) | \
54 #define TLP_CFG_DW1(pcie, tag, be) \
55 (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
56 #define TLP_CFG_DW2(bus, dev, fn, offset) \
57 (((bus) << 24) | ((dev) << 19) | ((fn) << 16) | (offset))
59 #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
60 #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
61 #define TLP_HDR_SIZE 3
62 #define TLP_LOOP 20000
65 #define IS_ROOT_PORT(pcie, bdf) \
66 ((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
68 #define PCI_EXP_LNKSTA 18 /* Link Status */
69 #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
72 * struct intel_fpga_pcie - Intel FPGA PCIe controller state
73 * @bus: Pointer to the PCI bus
74 * @cra_base: The base address of CRA register space
75 * @hip_base: The base address of Rootport configuration space
76 * @first_busno: This driver supports multiple PCIe controllers.
77 * first_busno stores the bus number of the PCIe root-port
78 * number which may vary depending on the PCIe setup.
80 struct intel_fpga_pcie {
82 void __iomem *cra_base;
83 void __iomem *hip_base;
88 * Intel FPGA PCIe port uses BAR0 of RC's configuration space as the
89 * translation from PCI bus to native BUS. Entire DDR region is mapped
90 * into PCIe space using these registers, so it can be reached by DMA from
92 * The BAR0 of bridge should be hidden during enumeration to avoid the
93 * sizing and resource allocation by PCIe core.
95 static bool intel_fpga_pcie_hide_rc_bar(struct intel_fpga_pcie *pcie,
96 pci_dev_t bdf, int offset)
98 if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) == 0 &&
99 PCI_FUNC(bdf) == 0 && offset == PCI_BASE_ADDRESS_0)
105 static inline void cra_writel(struct intel_fpga_pcie *pcie, const u32 value,
108 writel(value, pcie->cra_base + reg);
111 static inline u32 cra_readl(struct intel_fpga_pcie *pcie, const u32 reg)
113 return readl(pcie->cra_base + reg);
116 static bool intel_fpga_pcie_link_up(struct intel_fpga_pcie *pcie)
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA))
119 & PCI_EXP_LNKSTA_DLLLA);
122 static bool intel_fpga_pcie_addr_valid(struct intel_fpga_pcie *pcie,
125 /* If there is no link, then there is no device */
126 if (!IS_ROOT_PORT(pcie, bdf) && !intel_fpga_pcie_link_up(pcie))
129 /* access only one slot on each root port */
130 if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) > 0)
133 if ((PCI_BUS(bdf) == pcie->first_busno + 1) && PCI_DEV(bdf) > 0)
139 static void tlp_write_tx(struct intel_fpga_pcie *pcie, u32 reg0, u32 ctrl)
141 cra_writel(pcie, reg0, RP_TX_REG0);
142 cra_writel(pcie, ctrl, RP_TX_CNTRL);
145 static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value)
153 for (i = 0; i < TLP_LOOP; i++) {
154 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
155 if (!(ctrl & RP_RXCPL_SOP))
159 dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
162 for (i = 0; i < TLP_LOOP; i++) {
163 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
164 dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
165 if (ctrl & RP_RXCPL_EOP) {
166 comp_status = TLP_COMP_STATUS(dw[1]);
168 *value = pci_get_ff(PCI_SIZE_32);
173 TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
184 dev_err(pcie->dev, "read TLP packet timed out\n");
188 static void tlp_write_packet(struct intel_fpga_pcie *pcie, u32 *headers,
191 tlp_write_tx(pcie, headers[0], RP_TX_SOP);
193 tlp_write_tx(pcie, headers[1], 0);
195 tlp_write_tx(pcie, headers[2], 0);
197 tlp_write_tx(pcie, data, RP_TX_EOP);
200 static int tlp_cfg_dword_read(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
201 int offset, u8 byte_en, u32 *value)
203 u32 headers[TLP_HDR_SIZE];
204 u8 busno = PCI_BUS(bdf);
206 headers[0] = TLP_CFGRD_DW0(pcie, busno);
207 headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
208 headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
210 tlp_write_packet(pcie, headers, 0);
212 return tlp_read_packet(pcie, value);
215 static int tlp_cfg_dword_write(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
216 int offset, u8 byte_en, u32 value)
218 u32 headers[TLP_HDR_SIZE];
219 u8 busno = PCI_BUS(bdf);
221 headers[0] = TLP_CFGWR_DW0(pcie, busno);
222 headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
223 headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
225 tlp_write_packet(pcie, headers, value);
227 return tlp_read_packet(pcie, NULL);
230 int intel_fpga_rp_conf_addr(const struct udevice *bus, pci_dev_t bdf,
231 uint offset, void **paddress)
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus);
235 *paddress = RP_CFG_ADDR(pcie, offset);
240 static int intel_fpga_pcie_rp_rd_conf(struct udevice *bus, pci_dev_t bdf,
241 uint offset, ulong *valuep,
242 enum pci_size_t size)
244 return pci_generic_mmap_read_config(bus, intel_fpga_rp_conf_addr,
245 bdf, offset, valuep, size);
248 static int intel_fpga_pcie_rp_wr_conf(struct udevice *bus, pci_dev_t bdf,
249 uint offset, ulong value,
250 enum pci_size_t size)
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus);
255 ret = pci_generic_mmap_write_config(bus, intel_fpga_rp_conf_addr,
256 bdf, offset, value, size);
258 /* Monitor changes to PCI_PRIMARY_BUS register on root port
259 * and update local copy of root bus number accordingly.
261 if (offset == PCI_PRIMARY_BUS)
262 pcie->first_busno = (u8)(value);
268 static u8 pcie_get_byte_en(uint offset, enum pci_size_t size)
272 return 1 << (offset & 3);
274 return 3 << (offset & 3);
280 static int _pcie_intel_fpga_read_config(struct intel_fpga_pcie *pcie,
281 pci_dev_t bdf, uint offset,
282 ulong *valuep, enum pci_size_t size)
288 /* Uses memory mapped method to read rootport config registers */
289 if (IS_ROOT_PORT(pcie, bdf))
290 return intel_fpga_pcie_rp_rd_conf(pcie->bus, bdf,
291 offset, valuep, size);
293 byte_en = pcie_get_byte_en(offset, size);
294 ret = tlp_cfg_dword_read(pcie, bdf, offset & ~DWORD_MASK,
299 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
301 *valuep = pci_conv_32_to_size(data, offset, size);
306 static int _pcie_intel_fpga_write_config(struct intel_fpga_pcie *pcie,
307 pci_dev_t bdf, uint offset,
308 ulong value, enum pci_size_t size)
313 dev_dbg(pcie->dev, "PCIE CFG write: (b.d.f)=(%02d.%02d.%02d)\n",
314 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
315 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
316 offset, size, value);
318 /* Uses memory mapped method to read rootport config registers */
319 if (IS_ROOT_PORT(pcie, bdf))
320 return intel_fpga_pcie_rp_wr_conf(pcie->bus, bdf, offset,
323 byte_en = pcie_get_byte_en(offset, size);
324 data = pci_conv_size_to_32(0, value, offset, size);
326 return tlp_cfg_dword_write(pcie, bdf, offset & ~DWORD_MASK,
330 static int pcie_intel_fpga_read_config(const struct udevice *bus, pci_dev_t bdf,
331 uint offset, ulong *valuep,
332 enum pci_size_t size)
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus);
336 dev_dbg(pcie->dev, "PCIE CFG read: (b.d.f)=(%02d.%02d.%02d)\n",
337 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
339 if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset)) {
340 *valuep = (u32)pci_get_ff(size);
344 if (!intel_fpga_pcie_addr_valid(pcie, bdf)) {
345 *valuep = (u32)pci_get_ff(size);
349 return _pcie_intel_fpga_read_config(pcie, bdf, offset, valuep, size);
352 static int pcie_intel_fpga_write_config(struct udevice *bus, pci_dev_t bdf,
353 uint offset, ulong value,
354 enum pci_size_t size)
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus);
358 if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset))
361 if (!intel_fpga_pcie_addr_valid(pcie, bdf))
364 return _pcie_intel_fpga_write_config(pcie, bdf, offset, value,
368 static int pcie_intel_fpga_probe(struct udevice *dev)
370 struct intel_fpga_pcie *pcie = dev_get_priv(dev);
372 pcie->bus = pci_get_controller(dev);
373 pcie->first_busno = dev->seq;
375 /* clear all interrupts */
376 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
377 /* disable all interrupts */
378 cra_writel(pcie, 0, P2A_INT_ENABLE);
383 static int pcie_intel_fpga_ofdata_to_platdata(struct udevice *dev)
385 struct intel_fpga_pcie *pcie = dev_get_priv(dev);
386 struct fdt_resource reg_res;
387 int node = dev_of_offset(dev);
390 DECLARE_GLOBAL_DATA_PTR;
392 ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
395 dev_err(dev, "resource \"Cra\" not found\n");
399 pcie->cra_base = map_physmem(reg_res.start,
400 fdt_resource_size(®_res),
403 ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
406 dev_err(dev, "resource \"Hip\" not found\n");
410 pcie->hip_base = map_physmem(reg_res.start,
411 fdt_resource_size(®_res),
417 static const struct dm_pci_ops pcie_intel_fpga_ops = {
418 .read_config = pcie_intel_fpga_read_config,
419 .write_config = pcie_intel_fpga_write_config,
422 static const struct udevice_id pcie_intel_fpga_ids[] = {
423 { .compatible = "altr,pcie-root-port-2.0" },
427 U_BOOT_DRIVER(pcie_intel_fpga) = {
428 .name = "pcie_intel_fpga",
430 .of_match = pcie_intel_fpga_ids,
431 .ops = &pcie_intel_fpga_ops,
432 .ofdata_to_platdata = pcie_intel_fpga_ofdata_to_platdata,
433 .probe = pcie_intel_fpga_probe,
434 .priv_auto_alloc_size = sizeof(struct intel_fpga_pcie),