1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale i.MX6 PCI Express Root-Complex driver
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
7 * Based on upstream Linux kernel driver:
8 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
9 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/crm_regs.h>
20 #include <linux/sizes.h>
22 #include <asm/arch/sys_proto.h>
24 #define PCI_ACCESS_READ 0
25 #define PCI_ACCESS_WRITE 1
28 #define MX6_DBI_ADDR 0x08ffc000
29 #define MX6_IO_ADDR 0x08000000
30 #define MX6_MEM_ADDR 0x08100000
31 #define MX6_ROOT_ADDR 0x08f00000
33 #define MX6_DBI_ADDR 0x01ffc000
34 #define MX6_IO_ADDR 0x01000000
35 #define MX6_MEM_ADDR 0x01100000
36 #define MX6_ROOT_ADDR 0x01f00000
38 #define MX6_DBI_SIZE 0x4000
39 #define MX6_IO_SIZE 0x100000
40 #define MX6_MEM_SIZE 0xe00000
41 #define MX6_ROOT_SIZE 0xfc000
43 /* PCIe Port Logic registers (memory-mapped) */
44 #define PL_OFFSET 0x700
45 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
46 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
47 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
48 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
49 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
50 #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
51 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
53 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
54 #define PCIE_PHY_CTRL_DATA_LOC 0
55 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
56 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
57 #define PCIE_PHY_CTRL_WR_LOC 18
58 #define PCIE_PHY_CTRL_RD_LOC 19
60 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
61 #define PCIE_PHY_STAT_DATA_LOC 0
62 #define PCIE_PHY_STAT_ACK_LOC 16
64 /* PHY registers (not memory-mapped) */
65 #define PCIE_PHY_RX_ASIC_OUT 0x100D
67 #define PHY_RX_OVRD_IN_LO 0x1005
68 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
69 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
71 #define PCIE_PHY_PUP_REQ (1 << 7)
74 #define PCIE_ATU_VIEWPORT 0x900
75 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
76 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
77 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
78 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
79 #define PCIE_ATU_CR1 0x904
80 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
81 #define PCIE_ATU_TYPE_IO (0x2 << 0)
82 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
83 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
84 #define PCIE_ATU_CR2 0x908
85 #define PCIE_ATU_ENABLE (0x1 << 31)
86 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
87 #define PCIE_ATU_LOWER_BASE 0x90C
88 #define PCIE_ATU_UPPER_BASE 0x910
89 #define PCIE_ATU_LIMIT 0x914
90 #define PCIE_ATU_LOWER_TARGET 0x918
91 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
92 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
93 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
94 #define PCIE_ATU_UPPER_TARGET 0x91C
96 struct imx_pcie_priv {
97 void __iomem *dbi_base;
98 void __iomem *cfg_base;
102 * PHY access functions
104 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
107 u32 max_iterations = 10;
108 u32 wait_counter = 0;
111 val = readl(dbi_base + PCIE_PHY_STAT);
112 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
119 } while (wait_counter < max_iterations);
124 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
129 val = addr << PCIE_PHY_CTRL_DATA_LOC;
130 writel(val, dbi_base + PCIE_PHY_CTRL);
132 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
133 writel(val, dbi_base + PCIE_PHY_CTRL);
135 ret = pcie_phy_poll_ack(dbi_base, 1);
139 val = addr << PCIE_PHY_CTRL_DATA_LOC;
140 writel(val, dbi_base + PCIE_PHY_CTRL);
142 ret = pcie_phy_poll_ack(dbi_base, 0);
149 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
150 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
155 ret = pcie_phy_wait_ack(dbi_base, addr);
159 /* assert Read signal */
160 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
161 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
163 ret = pcie_phy_poll_ack(dbi_base, 1);
167 val = readl(dbi_base + PCIE_PHY_STAT);
168 *data = val & 0xffff;
170 /* deassert Read signal */
171 writel(0x00, dbi_base + PCIE_PHY_CTRL);
173 ret = pcie_phy_poll_ack(dbi_base, 0);
180 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
187 ret = pcie_phy_wait_ack(dbi_base, addr);
191 var = data << PCIE_PHY_CTRL_DATA_LOC;
192 writel(var, dbi_base + PCIE_PHY_CTRL);
195 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
196 writel(var, dbi_base + PCIE_PHY_CTRL);
198 ret = pcie_phy_poll_ack(dbi_base, 1);
202 /* deassert cap data */
203 var = data << PCIE_PHY_CTRL_DATA_LOC;
204 writel(var, dbi_base + PCIE_PHY_CTRL);
206 /* wait for ack de-assertion */
207 ret = pcie_phy_poll_ack(dbi_base, 0);
211 /* assert wr signal */
212 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
213 writel(var, dbi_base + PCIE_PHY_CTRL);
216 ret = pcie_phy_poll_ack(dbi_base, 1);
220 /* deassert wr signal */
221 var = data << PCIE_PHY_CTRL_DATA_LOC;
222 writel(var, dbi_base + PCIE_PHY_CTRL);
224 /* wait for ack de-assertion */
225 ret = pcie_phy_poll_ack(dbi_base, 0);
229 writel(0x0, dbi_base + PCIE_PHY_CTRL);
234 static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
239 /* link is debug bit 36, debug register 1 starts at bit 32 */
240 rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
241 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
242 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
246 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
247 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
248 * If (MAC/LTSSM.state == Recovery.RcvrLock)
249 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
252 pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
253 ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
261 printf("transition to gen2 is stuck, reset PHY!\n");
263 pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
264 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
265 pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
269 pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
270 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
271 pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
279 static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
282 * i.MX6 defines 16MB in the AXI address map for PCIe.
284 * That address space excepted the pcie registers is
285 * split and defined into different regions by iATU,
286 * with sizes and offsets as follows:
288 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
289 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
290 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
293 /* CMD reg:I/O space, MEM space, and Bus Master Enable */
294 setbits_le32(priv->dbi_base + PCI_COMMAND,
295 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
297 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
298 setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
299 PCI_CLASS_BRIDGE_PCI << 16);
301 /* Region #0 is used for Outbound CFG space access. */
302 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
304 writel(lower_32_bits((uintptr_t)priv->cfg_base),
305 priv->dbi_base + PCIE_ATU_LOWER_BASE);
306 writel(upper_32_bits((uintptr_t)priv->cfg_base),
307 priv->dbi_base + PCIE_ATU_UPPER_BASE);
308 writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
309 priv->dbi_base + PCIE_ATU_LIMIT);
311 writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
312 writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
313 writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
314 writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
320 * PCI Express accessors
322 static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
323 pci_dev_t d, int where)
325 void __iomem *va_address;
327 /* Reconfigure Region #0 */
328 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
331 writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
333 writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
335 if (PCI_BUS(d) == 0) {
336 va_address = priv->dbi_base;
338 writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
339 va_address = priv->cfg_base;
342 va_address += (where & ~0x3);
347 static int imx_pcie_addr_valid(pci_dev_t d)
349 if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
351 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
357 * Replace the original ARM DABT handler with a simple jump-back one.
359 * The problem here is that if we have a PCIe bridge attached to this PCIe
360 * controller, but no PCIe device is connected to the bridges' downstream
361 * port, the attempt to read/write from/to the config space will produce
362 * a DABT. This is a behavior of the controller and can not be disabled
365 * To work around the problem, we backup the current DABT handler address
366 * and replace it with our own DABT handler, which only bounces right back
369 static void imx_pcie_fix_dabt_handler(bool set)
371 extern uint32_t *_data_abort;
372 uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
374 static const uint32_t data_abort_bounce_handler = 0xe25ef004;
375 uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
377 static uint32_t data_abort_backup;
380 data_abort_backup = *data_abort_addr;
381 *data_abort_addr = data_abort_bounce_addr;
383 *data_abort_addr = data_abort_backup;
387 static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
390 void __iomem *va_address;
393 ret = imx_pcie_addr_valid(d);
399 va_address = get_bus_address(priv, d, where);
402 * Read the PCIe config space. We must replace the DABT handler
403 * here in case we got data abort from the PCIe controller, see
404 * imx_pcie_fix_dabt_handler() description. Note that writing the
405 * "val" with valid value is also imperative here as in case we
406 * did got DABT, the val would contain random value.
408 imx_pcie_fix_dabt_handler(true);
409 writel(0xffffffff, val);
410 *val = readl(va_address);
411 imx_pcie_fix_dabt_handler(false);
416 static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
419 void __iomem *va_address = NULL;
422 ret = imx_pcie_addr_valid(d);
426 va_address = get_bus_address(priv, d, where);
429 * Write the PCIe config space. We must replace the DABT handler
430 * here in case we got data abort from the PCIe controller, see
431 * imx_pcie_fix_dabt_handler() description.
433 imx_pcie_fix_dabt_handler(true);
434 writel(val, va_address);
435 imx_pcie_fix_dabt_handler(false);
443 static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
444 bool prepare_for_boot)
446 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
449 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
451 #if defined(CONFIG_MX6SX)
452 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
454 /* SSP_EN is not used on MX6SX anymore */
455 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
456 /* Force PCIe PHY reset */
457 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
458 /* Power up PCIe PHY */
459 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
462 * If the bootloader already enabled the link we need some special
463 * handling to get the core back into a state where it is safe to
464 * touch it for configuration. As there is no dedicated reset signal
465 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
466 * state before completely disabling LTSSM, which is a prerequisite
467 * for core configuration.
469 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
470 * indication that the bootloader activated the link.
472 if (is_mx6dq() && prepare_for_boot) {
473 u32 val, gpr1, gpr12;
475 gpr1 = readl(&iomuxc_regs->gpr[1]);
476 gpr12 = readl(&iomuxc_regs->gpr[12]);
477 if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
478 (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
479 val = readl(priv->dbi_base + PCIE_PL_PFLR);
480 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
481 val |= PCIE_PL_PFLR_FORCE_LINK;
483 imx_pcie_fix_dabt_handler(true);
484 writel(val, priv->dbi_base + PCIE_PL_PFLR);
485 imx_pcie_fix_dabt_handler(false);
487 gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
488 writel(val, &iomuxc_regs->gpr[12]);
491 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
492 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
498 static int imx6_pcie_init_phy(void)
500 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
502 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
504 clrsetbits_le32(&iomuxc_regs->gpr[12],
505 IOMUXC_GPR12_DEVICE_TYPE_MASK,
506 IOMUXC_GPR12_DEVICE_TYPE_RC);
507 clrsetbits_le32(&iomuxc_regs->gpr[12],
508 IOMUXC_GPR12_LOS_LEVEL_MASK,
509 IOMUXC_GPR12_LOS_LEVEL_9);
512 clrsetbits_le32(&iomuxc_regs->gpr[12],
513 IOMUXC_GPR12_RX_EQ_MASK,
514 IOMUXC_GPR12_RX_EQ_2);
517 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
518 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
519 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
520 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
521 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
522 &iomuxc_regs->gpr[8]);
527 __weak int imx6_pcie_toggle_power(void)
529 #ifdef CONFIG_PCIE_IMX_POWER_GPIO
530 gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
531 gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
533 gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
535 gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
540 __weak int imx6_pcie_toggle_reset(void)
543 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
544 * for detailed understanding of the PCIe CR reset logic.
546 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
547 * design does not conform to the specification. You must wait at
548 * least 20 ms after de-asserting the #PERST so the EP device can
549 * do self-initialisation.
551 * In case your #PERST pin is connected to a plain GPIO pin of the
552 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
553 * configuration file and the condition below will handle the rest
554 * of the reset toggling.
556 * In case your #PERST toggling logic is more complex, for example
557 * connected via CPLD or somesuch, you can override this function
558 * in your board file and implement reset logic as needed. You must
559 * not forget to wait at least 20 ms after de-asserting #PERST in
560 * this case either though.
562 * In case your #PERST line of the PCIe EP device is not connected
563 * at all, your design is broken and you should fix your design,
564 * otherwise you will observe problems like for example the link
565 * not coming up after rebooting the system back from running Linux
566 * that uses the PCIe as well OR the PCIe link might not come up in
567 * Linux at all in the first place since it's in some non-reset
568 * state due to being previously used in U-Boot.
570 #ifdef CONFIG_PCIE_IMX_PERST_GPIO
571 gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
572 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
574 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
576 gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
578 puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
583 static int imx6_pcie_deassert_core_reset(void)
585 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
587 imx6_pcie_toggle_power();
592 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
595 * Wait for the clock to settle a bit, when the clock are sourced
596 * from the CPU, we need about 30 ms to settle.
600 #if defined(CONFIG_MX6SX)
601 /* SSP_EN is not used on MX6SX anymore */
602 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
603 /* Clear PCIe PHY reset bit */
604 clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
607 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
608 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
611 imx6_pcie_toggle_reset();
616 static int imx_pcie_link_up(struct imx_pcie_priv *priv)
618 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
622 imx6_pcie_assert_core_reset(priv, false);
623 imx6_pcie_init_phy();
624 imx6_pcie_deassert_core_reset();
626 imx_pcie_regions_setup(priv);
629 * By default, the subordinate is set equally to the secondary
630 * bus (0x01) when the RC boots.
631 * This means that theoretically, only bus 1 is reachable from the RC.
632 * Force the PCIe RC subordinate to 0xff, otherwise no downstream
633 * devices will be detected if the enumeration is applied strictly.
635 tmp = readl(priv->dbi_base + 0x18);
637 writel(tmp, priv->dbi_base + 0x18);
640 * FIXME: Force the PCIe RC to Gen1 operation
641 * The RC must be forced into Gen1 mode before bringing the link
642 * up, otherwise no downstream devices are detected. After the
643 * link is up, a managed Gen1->Gen2 transition can be initiated.
645 tmp = readl(priv->dbi_base + 0x7c);
648 writel(tmp, priv->dbi_base + 0x7c);
650 /* LTSSM enable, starting link. */
651 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
653 while (!imx6_pcie_link_up(priv)) {
657 #ifdef CONFIG_PCI_SCAN_SHOW
658 puts("PCI: pcie phy link never came up\n");
660 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
661 readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
662 readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
670 #if !CONFIG_IS_ENABLED(DM_PCI)
671 static struct imx_pcie_priv imx_pcie_priv = {
672 .dbi_base = (void __iomem *)MX6_DBI_ADDR,
673 .cfg_base = (void __iomem *)MX6_ROOT_ADDR,
676 static struct imx_pcie_priv *priv = &imx_pcie_priv;
678 static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
681 struct imx_pcie_priv *priv = hose->priv_data;
683 return imx_pcie_read_cfg(priv, d, where, val);
686 static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
689 struct imx_pcie_priv *priv = hose->priv_data;
691 return imx_pcie_write_cfg(priv, d, where, val);
694 void imx_pcie_init(void)
696 /* Static instance of the controller. */
697 static struct pci_controller pcc;
698 struct pci_controller *hose = &pcc;
701 memset(&pcc, 0, sizeof(pcc));
703 hose->priv_data = priv;
706 pci_set_region(&hose->regions[0],
707 MX6_IO_ADDR, MX6_IO_ADDR,
708 MX6_IO_SIZE, PCI_REGION_IO);
710 /* PCI memory space */
711 pci_set_region(&hose->regions[1],
712 MX6_MEM_ADDR, MX6_MEM_ADDR,
713 MX6_MEM_SIZE, PCI_REGION_MEM);
715 /* System memory space */
716 pci_set_region(&hose->regions[2],
717 MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
718 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
720 hose->region_count = 3;
723 pci_hose_read_config_byte_via_dword,
724 pci_hose_read_config_word_via_dword,
725 imx_pcie_read_config,
726 pci_hose_write_config_byte_via_dword,
727 pci_hose_write_config_word_via_dword,
728 imx_pcie_write_config);
730 /* Start the controller. */
731 ret = imx_pcie_link_up(priv);
734 pci_register_hose(hose);
735 hose->last_busno = pci_hose_scan(hose);
739 void imx_pcie_remove(void)
741 imx6_pcie_assert_core_reset(priv, true);
744 /* Probe function. */
745 void pci_init_board(void)
750 static int imx_pcie_dm_read_config(struct udevice *dev, pci_dev_t bdf,
751 uint offset, ulong *value,
752 enum pci_size_t size)
754 struct imx_pcie_priv *priv = dev_get_priv(dev);
758 ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
762 *value = pci_conv_32_to_size(tmpval, offset, size);
766 static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
767 uint offset, ulong value,
768 enum pci_size_t size)
770 struct imx_pcie_priv *priv = dev_get_priv(dev);
774 ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
778 newval = pci_conv_size_to_32(tmpval, value, offset, size);
779 return imx_pcie_write_cfg(priv, bdf, offset, newval);
782 static int imx_pcie_dm_probe(struct udevice *dev)
784 struct imx_pcie_priv *priv = dev_get_priv(dev);
786 return imx_pcie_link_up(priv);
789 static int imx_pcie_dm_remove(struct udevice *dev)
791 struct imx_pcie_priv *priv = dev_get_priv(dev);
793 imx6_pcie_assert_core_reset(priv, true);
798 static int imx_pcie_ofdata_to_platdata(struct udevice *dev)
800 struct imx_pcie_priv *priv = dev_get_priv(dev);
802 priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
803 priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
804 if (!priv->dbi_base || !priv->cfg_base)
810 static const struct dm_pci_ops imx_pcie_ops = {
811 .read_config = imx_pcie_dm_read_config,
812 .write_config = imx_pcie_dm_write_config,
815 static const struct udevice_id imx_pcie_ids[] = {
816 { .compatible = "fsl,imx6q-pcie" },
820 U_BOOT_DRIVER(imx_pcie) = {
823 .of_match = imx_pcie_ids,
824 .ops = &imx_pcie_ops,
825 .probe = imx_pcie_dm_probe,
826 .remove = imx_pcie_dm_remove,
827 .ofdata_to_platdata = imx_pcie_ofdata_to_platdata,
828 .priv_auto_alloc_size = sizeof(struct imx_pcie_priv),
829 .flags = DM_FLAG_OS_PREPARE,