1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * PCIe DM U-Boot driver for Freescale PowerPC SoCs
6 * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
13 #define CSR_CLASSCODE 0x474
15 #ifdef CONFIG_SYS_FSL_PCI_VER_3_X
16 #define FSL_PCIE_CAP_ID 0x70
18 #define FSL_PCIE_CAP_ID 0x4c
20 /* PCIe Device Control Register */
21 #define PCI_DCR (FSL_PCIE_CAP_ID + 0x08)
22 /* PCIe Device Status Register */
23 #define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a)
24 /* PCIe Link Control Register */
25 #define PCI_LCR (FSL_PCIE_CAP_ID + 0x10)
26 /* PCIe Link Status Register */
27 #define PCI_LSR (FSL_PCIE_CAP_ID + 0x12)
29 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
30 #define CONFIG_SYS_PCI_MEMORY_BUS 0
33 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
34 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
37 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
38 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024)
41 #define PEX_CSR0_LTSSM_MASK 0xFC
42 #define PEX_CSR0_LTSSM_SHIFT 2
43 #define LTSSM_L0_REV3 0x11
46 struct fsl_pcie_data {
47 u32 block_offset; /* Offset from CCSR of 1st controller */
48 u32 block_offset_mask; /* Mask out the CCSR base */
49 u32 stride; /* Offset stride between controllers */
56 u32 law_trgt_if; /* LAW target ID */
57 u32 block_rev; /* IP block revision */
58 bool mode; /* RC&EP mode flag */
59 bool enabled; /* Enable status */
60 struct list_head list;
61 struct fsl_pcie_data *info;
64 extern struct list_head fsl_pcie_list;
66 #endif /* _PCIE_FSL_H_ */