1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell MVEBU SoCs
5 * Based on Barebox drivers/pci/pci-mvebu.c
8 * Anton Schubert <anton.schubert@gmx.de>
9 * Stefan Roese <sr@denx.de>
15 #include <dm/device-internal.h>
17 #include <dm/of_access.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/soc.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/mbus.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 /* PCIe unit register offsets */
29 #define SELECT(x, n) ((x >> n) & 1UL)
31 #define PCIE_DEV_ID_OFF 0x0000
32 #define PCIE_CMD_OFF 0x0004
33 #define PCIE_DEV_REV_OFF 0x0008
34 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
35 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
36 #define PCIE_CAPAB_OFF 0x0060
37 #define PCIE_CTRL_STAT_OFF 0x0068
38 #define PCIE_HEADER_LOG_4_OFF 0x0128
39 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
40 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
41 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
42 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
43 #define PCIE_WIN5_CTRL_OFF 0x1880
44 #define PCIE_WIN5_BASE_OFF 0x1884
45 #define PCIE_WIN5_REMAP_OFF 0x188c
46 #define PCIE_CONF_ADDR_OFF 0x18f8
47 #define PCIE_CONF_ADDR_EN BIT(31)
48 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
49 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
50 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
51 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
52 #define PCIE_CONF_ADDR(dev, reg) \
53 (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
54 PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
56 #define PCIE_CONF_DATA_OFF 0x18fc
57 #define PCIE_MASK_OFF 0x1910
58 #define PCIE_MASK_ENABLE_INTS (0xf << 24)
59 #define PCIE_CTRL_OFF 0x1a00
60 #define PCIE_CTRL_X1_MODE BIT(0)
61 #define PCIE_STAT_OFF 0x1a04
62 #define PCIE_STAT_BUS (0xff << 8)
63 #define PCIE_STAT_DEV (0x1f << 16)
64 #define PCIE_STAT_LINK_DOWN BIT(0)
65 #define PCIE_DEBUG_CTRL 0x1a60
66 #define PCIE_DEBUG_SOFT_RESET BIT(20)
69 struct pci_controller hose;
71 void __iomem *membase;
80 unsigned int mem_target;
81 unsigned int mem_attr;
85 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
86 * into SoCs address space. Each controller will map 128M of MEM
87 * and 64K of I/O space when registered.
89 static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
90 #define PCIE_MEM_SIZE (128 << 20)
92 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
95 val = readl(pcie->base + PCIE_STAT_OFF);
96 return !(val & PCIE_STAT_LINK_DOWN);
99 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
103 stat = readl(pcie->base + PCIE_STAT_OFF);
104 stat &= ~PCIE_STAT_BUS;
106 writel(stat, pcie->base + PCIE_STAT_OFF);
109 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
113 stat = readl(pcie->base + PCIE_STAT_OFF);
114 stat &= ~PCIE_STAT_DEV;
116 writel(stat, pcie->base + PCIE_STAT_OFF);
119 static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
123 stat = readl(pcie->base + PCIE_STAT_OFF);
124 return (stat & PCIE_STAT_BUS) >> 8;
127 static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
131 stat = readl(pcie->base + PCIE_STAT_OFF);
132 return (stat & PCIE_STAT_DEV) >> 16;
135 static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
137 return container_of(hose, struct mvebu_pcie, hose);
140 static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
141 uint offset, ulong *valuep,
142 enum pci_size_t size)
144 struct mvebu_pcie *pcie = dev_get_platdata(bus);
145 int local_bus = PCI_BUS(pcie->dev);
146 int local_dev = PCI_DEV(pcie->dev);
150 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
151 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
153 /* Only allow one other device besides the local one on the local bus */
154 if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
155 if (local_dev == 0 && PCI_DEV(bdf) != 1) {
156 debug("- out of range\n");
158 * If local dev is 0, the first other dev can
161 *valuep = pci_get_ff(size);
163 } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
164 debug("- out of range\n");
166 * If local dev is not 0, the first other dev can
169 *valuep = pci_get_ff(size);
175 reg = PCIE_CONF_ADDR(bdf, offset);
176 writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
177 data = readl(pcie->base + PCIE_CONF_DATA_OFF);
178 debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data);
179 *valuep = pci_conv_32_to_size(data, offset, size);
184 static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
185 uint offset, ulong value,
186 enum pci_size_t size)
188 struct mvebu_pcie *pcie = dev_get_platdata(bus);
189 int local_bus = PCI_BUS(pcie->dev);
190 int local_dev = PCI_DEV(pcie->dev);
193 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
194 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
195 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
197 /* Only allow one other device besides the local one on the local bus */
198 if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
199 if (local_dev == 0 && PCI_DEV(bdf) != 1) {
201 * If local dev is 0, the first other dev can
205 } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
207 * If local dev is not 0, the first other dev can
214 writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
215 data = pci_conv_size_to_32(0, value, offset, size);
216 writel(data, pcie->base + PCIE_CONF_DATA_OFF);
222 * Setup PCIE BARs and Address Decode Wins:
223 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
224 * WIN[0-3] -> DRAM bank[0-3]
226 static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
228 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
232 /* First, disable and clear BARs and windows. */
233 for (i = 1; i < 3; i++) {
234 writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
235 writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
236 writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
239 for (i = 0; i < 5; i++) {
240 writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
241 writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
242 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
245 writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
246 writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
247 writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
249 /* Setup windows for DDR banks. Count total DDR size on the fly. */
251 for (i = 0; i < dram->num_cs; i++) {
252 const struct mbus_dram_window *cs = dram->cs + i;
254 writel(cs->base & 0xffff0000,
255 pcie->base + PCIE_WIN04_BASE_OFF(i));
256 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
257 writel(((cs->size - 1) & 0xffff0000) |
258 (cs->mbus_attr << 8) |
259 (dram->mbus_dram_target_id << 4) | 1,
260 pcie->base + PCIE_WIN04_CTRL_OFF(i));
265 /* Round up 'size' to the nearest power of two. */
266 if ((size & (size - 1)) != 0)
267 size = 1 << fls(size);
269 /* Setup BAR[1] to all DRAM banks. */
270 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
271 writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
272 writel(((size - 1) & 0xffff0000) | 0x1,
273 pcie->base + PCIE_BAR_CTRL_OFF(1));
276 static int mvebu_pcie_probe(struct udevice *dev)
278 struct mvebu_pcie *pcie = dev_get_platdata(dev);
279 struct udevice *ctlr = pci_get_controller(dev);
280 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
284 debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
285 pcie->port, pcie->lane, (u32)pcie->base);
287 /* Read Id info and local bus/dev */
288 debug("direct conf read %08x, local bus %d, local dev %d\n",
289 readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
290 mvebu_pcie_get_local_dev_nr(pcie));
292 mvebu_pcie_set_local_bus_nr(pcie, bus);
293 mvebu_pcie_set_local_dev_nr(pcie, 0);
294 pcie->dev = PCI_BDF(bus, 0, 0);
296 pcie->mem.start = (u32)mvebu_pcie_membase;
297 pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
298 mvebu_pcie_membase += PCIE_MEM_SIZE;
300 if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
301 (phys_addr_t)pcie->mem.start,
303 printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
304 (u32)pcie->mem.start, PCIE_MEM_SIZE);
307 /* Setup windows and configure host bridge */
308 mvebu_pcie_setup_wins(pcie);
310 /* Master + slave enable. */
311 reg = readl(pcie->base + PCIE_CMD_OFF);
312 reg |= PCI_COMMAND_MEMORY;
313 reg |= PCI_COMMAND_MASTER;
314 reg |= BIT(10); /* disable interrupts */
315 writel(reg, pcie->base + PCIE_CMD_OFF);
317 /* PCI memory space */
318 pci_set_region(hose->regions + 0, pcie->mem.start,
319 pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
320 pci_set_region(hose->regions + 1,
323 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
324 hose->region_count = 2;
326 /* Set BAR0 to internal registers */
327 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
328 writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
335 static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
340 addr = ofnode_get_property(node, "assigned-addresses", &len);
342 pr_err("property \"assigned-addresses\" not found");
343 return -FDT_ERR_NOTFOUND;
346 pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
351 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
352 #define DT_TYPE_IO 0x1
353 #define DT_TYPE_MEM32 0x2
354 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
355 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
357 static int mvebu_get_tgt_attr(ofnode node, int devfn,
362 const int na = 3, ns = 2;
364 int rlen, nranges, rangesz, pna, i;
369 range = ofnode_get_property(node, "ranges", &rlen);
374 * Linux uses of_n_addr_cells() to get the number of address cells
375 * here. Currently this function is only available in U-Boot when
376 * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
377 * general, lets't hardcode the "pna" value in the U-Boot code.
379 pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
380 rangesz = pna + na + ns;
381 nranges = rlen / sizeof(__be32) / rangesz;
383 for (i = 0; i < nranges; i++, range += rangesz) {
384 u32 flags = of_read_number(range, 1);
385 u32 slot = of_read_number(range + 1, 1);
386 u64 cpuaddr = of_read_number(range + na, pna);
389 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
390 rtype = IORESOURCE_IO;
391 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
392 rtype = IORESOURCE_MEM;
397 * The Linux code used PCI_SLOT() here, which expects devfn
398 * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
399 * only expects devfn in 15..8, where its saved in this driver.
401 if (slot == PCI_DEV(devfn) && type == rtype) {
402 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
403 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
411 static int mvebu_pcie_ofdata_to_platdata(struct udevice *dev)
413 struct mvebu_pcie *pcie = dev_get_platdata(dev);
416 /* Get port number, lane number and memory target / attr */
417 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
423 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
426 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
428 /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
429 pcie->devfn = pci_get_devfn(dev);
430 if (pcie->devfn < 0) {
435 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
437 &pcie->mem_target, &pcie->mem_attr);
439 printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
443 /* Parse PCIe controller register base from DT */
444 ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
448 /* Check link and skip ports that have no link */
449 if (!mvebu_pcie_link_up(pcie)) {
450 debug("%s: %s - down\n", __func__, pcie->name);
461 static const struct dm_pci_ops mvebu_pcie_ops = {
462 .read_config = mvebu_pcie_read_config,
463 .write_config = mvebu_pcie_write_config,
466 static struct driver pcie_mvebu_drv = {
467 .name = "pcie_mvebu",
469 .ops = &mvebu_pcie_ops,
470 .probe = mvebu_pcie_probe,
471 .ofdata_to_platdata = mvebu_pcie_ofdata_to_platdata,
472 .platdata_auto_alloc_size = sizeof(struct mvebu_pcie),
476 * Use a MISC device to bind the n instances (child nodes) of the
477 * PCIe base controller in UCLASS_PCI.
479 static int mvebu_pcie_bind(struct udevice *parent)
481 struct mvebu_pcie *pcie;
482 struct uclass_driver *drv;
486 /* Lookup eth driver */
487 drv = lists_uclass_lookup(UCLASS_PCI);
489 puts("Cannot find PCI driver\n");
493 ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
494 if (!ofnode_is_available(subnode))
497 pcie = calloc(1, sizeof(*pcie));
501 /* Create child device UCLASS_PCI and bind it */
502 device_bind_ofnode(parent, &pcie_mvebu_drv, pcie->name, pcie,
509 static const struct udevice_id mvebu_pcie_ids[] = {
510 { .compatible = "marvell,armada-xp-pcie" },
511 { .compatible = "marvell,armada-370-pcie" },
515 U_BOOT_DRIVER(pcie_mvebu_base) = {
516 .name = "pcie_mvebu_base",
518 .of_match = mvebu_pcie_ids,
519 .bind = mvebu_pcie_bind,