1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI autoconfiguration library (legacy version, do not change)
5 * Author: Matt Porter <mporter@mvista.com>
7 * Copyright 2000 MontaVista Software Inc.
16 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
17 * and change pci_auto.c.
20 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
21 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
22 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
29 void pciauto_setup_device(struct pci_controller *hose,
30 pci_dev_t dev, int bars_num,
31 struct pci_region *mem,
32 struct pci_region *prefetch,
33 struct pci_region *io)
39 #ifndef CONFIG_PCI_ENUM_ONLY
43 struct pci_region *bar_res;
48 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
49 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
51 for (bar = PCI_BASE_ADDRESS_0;
52 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
53 /* Tickle the BAR and get the response */
54 #ifndef CONFIG_PCI_ENUM_ONLY
55 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
57 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
59 /* If BAR is not implemented go to the next BAR */
63 #ifndef CONFIG_PCI_ENUM_ONLY
67 /* Check the BAR type and set our address mask */
68 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
69 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
71 #ifndef CONFIG_PCI_ENUM_ONLY
75 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
76 bar_nr, (unsigned long long)bar_size);
78 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
79 PCI_BASE_ADDRESS_MEM_TYPE_64) {
80 u32 bar_response_upper;
83 #ifndef CONFIG_PCI_ENUM_ONLY
84 pci_hose_write_config_dword(hose, dev, bar + 4,
87 pci_hose_read_config_dword(hose, dev, bar + 4,
90 bar64 = ((u64)bar_response_upper << 32) | bar_response;
92 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
93 #ifndef CONFIG_PCI_ENUM_ONLY
97 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
99 #ifndef CONFIG_PCI_ENUM_ONLY
100 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
105 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
106 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
107 (unsigned long long)bar_size);
111 #ifndef CONFIG_PCI_ENUM_ONLY
112 if (pciauto_region_allocate(bar_res, bar_size,
113 &bar_value, found_mem64) == 0) {
114 /* Write it out and update our limit */
115 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
119 #ifdef CONFIG_SYS_PCI_64BIT
120 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
123 * If we are a 64-bit decoder then increment to the
124 * upper 32 bits of the bar and force it to locate
125 * in the lower 4GB of memory.
127 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
133 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
134 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
141 #ifndef CONFIG_PCI_ENUM_ONLY
142 /* Configure the expansion ROM address */
143 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
145 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
146 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
147 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
148 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
149 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
151 bar_size = -(bar_response & ~1);
152 debug("PCI Autoconfig: ROM, size=%#x, ",
153 (unsigned int)bar_size);
154 if (pciauto_region_allocate(mem, bar_size,
155 &bar_value, false) == 0) {
156 pci_hose_write_config_dword(hose, dev, rom_addr,
159 cmdstat |= PCI_COMMAND_MEMORY;
165 /* PCI_COMMAND_IO must be set for VGA device */
166 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
167 if (class == PCI_CLASS_DISPLAY_VGA)
168 cmdstat |= PCI_COMMAND_IO;
170 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
171 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
172 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
173 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
176 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
177 pci_dev_t dev, int sub_bus)
179 struct pci_region *pci_mem;
180 struct pci_region *pci_prefetch;
181 struct pci_region *pci_io;
182 u16 cmdstat, prefechable_64;
184 pci_mem = hose->pci_mem;
185 pci_prefetch = hose->pci_prefetch;
186 pci_io = hose->pci_io;
188 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
189 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
191 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
193 /* Configure bus number registers */
194 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
195 PCI_BUS(dev) - hose->first_busno);
196 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
197 sub_bus - hose->first_busno);
198 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
201 /* Round memory allocator to 1MB boundary */
202 pciauto_region_align(pci_mem, 0x100000);
204 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
205 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
206 (pci_mem->bus_lower & 0xfff00000) >> 16);
208 cmdstat |= PCI_COMMAND_MEMORY;
212 /* Round memory allocator to 1MB boundary */
213 pciauto_region_align(pci_prefetch, 0x100000);
215 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
216 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
217 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
218 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
219 #ifdef CONFIG_SYS_PCI_64BIT
220 pci_hose_write_config_dword(hose, dev,
221 PCI_PREF_BASE_UPPER32,
222 pci_prefetch->bus_lower >> 32);
224 pci_hose_write_config_dword(hose, dev,
225 PCI_PREF_BASE_UPPER32,
229 cmdstat |= PCI_COMMAND_MEMORY;
231 /* We don't support prefetchable memory for now, so disable */
232 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
233 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
234 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
235 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
236 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
241 /* Round I/O allocator to 4KB boundary */
242 pciauto_region_align(pci_io, 0x1000);
244 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
245 (pci_io->bus_lower & 0x0000f000) >> 8);
246 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
247 (pci_io->bus_lower & 0xffff0000) >> 16);
249 cmdstat |= PCI_COMMAND_IO;
252 /* Enable memory and I/O accesses, enable bus master */
253 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
254 cmdstat | PCI_COMMAND_MASTER);
257 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
258 pci_dev_t dev, int sub_bus)
260 struct pci_region *pci_mem;
261 struct pci_region *pci_prefetch;
262 struct pci_region *pci_io;
264 pci_mem = hose->pci_mem;
265 pci_prefetch = hose->pci_prefetch;
266 pci_io = hose->pci_io;
268 /* Configure bus number registers */
269 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
270 sub_bus - hose->first_busno);
273 /* Round memory allocator to 1MB boundary */
274 pciauto_region_align(pci_mem, 0x100000);
276 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
277 (pci_mem->bus_lower - 1) >> 16);
283 pci_hose_read_config_word(hose, dev,
284 PCI_PREF_MEMORY_LIMIT,
286 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
288 /* Round memory allocator to 1MB boundary */
289 pciauto_region_align(pci_prefetch, 0x100000);
291 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
292 (pci_prefetch->bus_lower - 1) >> 16);
293 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
294 #ifdef CONFIG_SYS_PCI_64BIT
295 pci_hose_write_config_dword(hose, dev,
296 PCI_PREF_LIMIT_UPPER32,
297 (pci_prefetch->bus_lower - 1) >> 32);
299 pci_hose_write_config_dword(hose, dev,
300 PCI_PREF_LIMIT_UPPER32,
306 /* Round I/O allocator to 4KB boundary */
307 pciauto_region_align(pci_io, 0x1000);
309 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
310 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
311 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
312 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
318 * HJF: Changed this to return int. I think this is required
319 * to get the correct result when scanning bridges
321 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
323 struct pci_region *pci_mem;
324 struct pci_region *pci_prefetch;
325 struct pci_region *pci_io;
326 unsigned int sub_bus = PCI_BUS(dev);
327 unsigned short class;
330 pci_mem = hose->pci_mem;
331 pci_prefetch = hose->pci_prefetch;
332 pci_io = hose->pci_io;
334 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
337 case PCI_CLASS_BRIDGE_PCI:
338 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
341 pciauto_setup_device(hose, dev, 2, pci_mem,
342 pci_prefetch, pci_io);
344 /* Passing in current_busno allows for sibling P2P bridges */
345 hose->current_busno++;
346 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
348 * need to figure out if this is a subordinate bridge on the bus
349 * to be able to properly set the pri/sec/sub bridge registers.
351 n = pci_hose_scan_bus(hose, hose->current_busno);
353 /* figure out the deepest we've gone for this leg */
354 sub_bus = max((unsigned int)n, sub_bus);
355 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
357 sub_bus = hose->current_busno;
360 case PCI_CLASS_BRIDGE_CARDBUS:
362 * just do a minimal setup of the bridge,
363 * let the OS take care of the rest
365 pciauto_setup_device(hose, dev, 0, pci_mem,
366 pci_prefetch, pci_io);
368 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
371 hose->current_busno++;
374 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
375 case PCI_CLASS_BRIDGE_OTHER:
376 debug("PCI Autoconfig: Skipping bridge device %d\n",
380 #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
381 !defined(CONFIG_TARGET_CADDY2)
382 case PCI_CLASS_BRIDGE_OTHER:
384 * The host/PCI bridge 1 seems broken in 8349 - it presents
385 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
386 * device claiming resources io/mem/irq.. we only allow for
387 * the PIMMR window to be allocated (BAR0 - 1MB size)
389 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
390 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
391 hose->pci_prefetch, hose->pci_io);
395 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
396 debug("PCI AutoConfig: Found PowerPC device\n");
399 pciauto_setup_device(hose, dev, 6, pci_mem,
400 pci_prefetch, pci_io);