2 * arch/powerpc/kernel/pci_auto.c
4 * PCI autoconfiguration library
6 * Author: Matt Porter <mporter@mvista.com>
8 * Copyright 2000 MontaVista Software Inc.
10 * SPDX-License-Identifier: GPL-2.0+
17 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
18 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
19 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
26 void pciauto_setup_device(struct pci_controller *hose,
27 pci_dev_t dev, int bars_num,
28 struct pci_region *mem,
29 struct pci_region *prefetch,
30 struct pci_region *io)
36 #ifndef CONFIG_PCI_ENUM_ONLY
40 struct pci_region *bar_res;
45 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
46 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
48 for (bar = PCI_BASE_ADDRESS_0;
49 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
50 /* Tickle the BAR and get the response */
51 #ifndef CONFIG_PCI_ENUM_ONLY
52 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
54 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
56 /* If BAR is not implemented go to the next BAR */
60 #ifndef CONFIG_PCI_ENUM_ONLY
64 /* Check the BAR type and set our address mask */
65 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
66 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
68 #ifndef CONFIG_PCI_ENUM_ONLY
72 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
73 bar_nr, (unsigned long long)bar_size);
75 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
76 PCI_BASE_ADDRESS_MEM_TYPE_64) {
77 u32 bar_response_upper;
80 #ifndef CONFIG_PCI_ENUM_ONLY
81 pci_hose_write_config_dword(hose, dev, bar + 4,
84 pci_hose_read_config_dword(hose, dev, bar + 4,
87 bar64 = ((u64)bar_response_upper << 32) | bar_response;
89 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
90 #ifndef CONFIG_PCI_ENUM_ONLY
94 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
96 #ifndef CONFIG_PCI_ENUM_ONLY
97 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
103 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
104 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
105 (unsigned long long)bar_size);
108 #ifndef CONFIG_PCI_ENUM_ONLY
109 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
110 /* Write it out and update our limit */
111 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
115 #ifdef CONFIG_SYS_PCI_64BIT
116 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
119 * If we are a 64-bit decoder then increment to the
120 * upper 32 bits of the bar and force it to locate
121 * in the lower 4GB of memory.
123 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
129 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
130 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
137 #ifndef CONFIG_PCI_ENUM_ONLY
138 /* Configure the expansion ROM address */
139 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
141 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
142 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
143 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
144 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
145 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
147 bar_size = -(bar_response & ~1);
148 debug("PCI Autoconfig: ROM, size=%#x, ",
149 (unsigned int)bar_size);
150 if (pciauto_region_allocate(mem, bar_size,
152 pci_hose_write_config_dword(hose, dev, rom_addr,
155 cmdstat |= PCI_COMMAND_MEMORY;
161 /* PCI_COMMAND_IO must be set for VGA device */
162 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
163 if (class == PCI_CLASS_DISPLAY_VGA)
164 cmdstat |= PCI_COMMAND_IO;
166 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
167 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
168 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
169 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
172 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
173 pci_dev_t dev, int sub_bus)
175 struct pci_region *pci_mem;
176 struct pci_region *pci_prefetch;
177 struct pci_region *pci_io;
178 u16 cmdstat, prefechable_64;
181 /* The root controller has the region information */
182 struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
184 pci_mem = ctlr_hose->pci_mem;
185 pci_prefetch = ctlr_hose->pci_prefetch;
186 pci_io = ctlr_hose->pci_io;
188 pci_mem = hose->pci_mem;
189 pci_prefetch = hose->pci_prefetch;
190 pci_io = hose->pci_io;
193 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
194 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
196 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
198 /* Configure bus number registers */
200 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
201 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
203 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
204 PCI_BUS(dev) - hose->first_busno);
205 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
206 sub_bus - hose->first_busno);
208 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
211 /* Round memory allocator to 1MB boundary */
212 pciauto_region_align(pci_mem, 0x100000);
214 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
215 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
216 (pci_mem->bus_lower & 0xfff00000) >> 16);
218 cmdstat |= PCI_COMMAND_MEMORY;
222 /* Round memory allocator to 1MB boundary */
223 pciauto_region_align(pci_prefetch, 0x100000);
225 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
226 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
227 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
228 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
229 #ifdef CONFIG_SYS_PCI_64BIT
230 pci_hose_write_config_dword(hose, dev,
231 PCI_PREF_BASE_UPPER32,
232 pci_prefetch->bus_lower >> 32);
234 pci_hose_write_config_dword(hose, dev,
235 PCI_PREF_BASE_UPPER32,
239 cmdstat |= PCI_COMMAND_MEMORY;
241 /* We don't support prefetchable memory for now, so disable */
242 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
243 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
244 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
245 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
246 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
251 /* Round I/O allocator to 4KB boundary */
252 pciauto_region_align(pci_io, 0x1000);
254 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
255 (pci_io->bus_lower & 0x0000f000) >> 8);
256 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
257 (pci_io->bus_lower & 0xffff0000) >> 16);
259 cmdstat |= PCI_COMMAND_IO;
262 /* Enable memory and I/O accesses, enable bus master */
263 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
264 cmdstat | PCI_COMMAND_MASTER);
267 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
268 pci_dev_t dev, int sub_bus)
270 struct pci_region *pci_mem;
271 struct pci_region *pci_prefetch;
272 struct pci_region *pci_io;
275 /* The root controller has the region information */
276 struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
278 pci_mem = ctlr_hose->pci_mem;
279 pci_prefetch = ctlr_hose->pci_prefetch;
280 pci_io = ctlr_hose->pci_io;
282 pci_mem = hose->pci_mem;
283 pci_prefetch = hose->pci_prefetch;
284 pci_io = hose->pci_io;
287 /* Configure bus number registers */
289 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
291 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
292 sub_bus - hose->first_busno);
296 /* Round memory allocator to 1MB boundary */
297 pciauto_region_align(pci_mem, 0x100000);
299 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
300 (pci_mem->bus_lower - 1) >> 16);
306 pci_hose_read_config_word(hose, dev,
307 PCI_PREF_MEMORY_LIMIT,
309 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
311 /* Round memory allocator to 1MB boundary */
312 pciauto_region_align(pci_prefetch, 0x100000);
314 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
315 (pci_prefetch->bus_lower - 1) >> 16);
316 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
317 #ifdef CONFIG_SYS_PCI_64BIT
318 pci_hose_write_config_dword(hose, dev,
319 PCI_PREF_LIMIT_UPPER32,
320 (pci_prefetch->bus_lower - 1) >> 32);
322 pci_hose_write_config_dword(hose, dev,
323 PCI_PREF_LIMIT_UPPER32,
329 /* Round I/O allocator to 4KB boundary */
330 pciauto_region_align(pci_io, 0x1000);
332 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
333 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
334 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
335 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
341 * HJF: Changed this to return int. I think this is required
342 * to get the correct result when scanning bridges
344 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
346 struct pci_region *pci_mem;
347 struct pci_region *pci_prefetch;
348 struct pci_region *pci_io;
349 unsigned int sub_bus = PCI_BUS(dev);
350 unsigned short class;
354 /* The root controller has the region information */
355 struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
357 pci_mem = ctlr_hose->pci_mem;
358 pci_prefetch = ctlr_hose->pci_prefetch;
359 pci_io = ctlr_hose->pci_io;
361 pci_mem = hose->pci_mem;
362 pci_prefetch = hose->pci_prefetch;
363 pci_io = hose->pci_io;
366 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
369 case PCI_CLASS_BRIDGE_PCI:
370 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
373 pciauto_setup_device(hose, dev, 2, pci_mem,
374 pci_prefetch, pci_io);
377 n = dm_pci_hose_probe_bus(hose, dev);
380 sub_bus = (unsigned int)n;
382 /* Passing in current_busno allows for sibling P2P bridges */
383 hose->current_busno++;
384 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
386 * need to figure out if this is a subordinate bridge on the bus
387 * to be able to properly set the pri/sec/sub bridge registers.
389 n = pci_hose_scan_bus(hose, hose->current_busno);
391 /* figure out the deepest we've gone for this leg */
392 sub_bus = max((unsigned int)n, sub_bus);
393 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
395 sub_bus = hose->current_busno;
399 case PCI_CLASS_BRIDGE_CARDBUS:
401 * just do a minimal setup of the bridge,
402 * let the OS take care of the rest
404 pciauto_setup_device(hose, dev, 0, pci_mem,
405 pci_prefetch, pci_io);
407 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
410 #ifndef CONFIG_DM_PCI
411 hose->current_busno++;
415 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
416 case PCI_CLASS_BRIDGE_OTHER:
417 debug("PCI Autoconfig: Skipping bridge device %d\n",
421 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
422 case PCI_CLASS_BRIDGE_OTHER:
424 * The host/PCI bridge 1 seems broken in 8349 - it presents
425 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
426 * device claiming resources io/mem/irq.. we only allow for
427 * the PIMMR window to be allocated (BAR0 - 1MB size)
429 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
430 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
431 hose->pci_prefetch, hose->pci_io);
435 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
436 debug("PCI AutoConfig: Found PowerPC device\n");
439 pciauto_setup_device(hose, dev, 6, pci_mem,
440 pci_prefetch, pci_io);