1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI autoconfiguration library (legacy version, do not change)
5 * Author: Matt Porter <mporter@mvista.com>
7 * Copyright 2000 MontaVista Software Inc.
15 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
16 * and change pci_auto.c.
19 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
20 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
21 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
28 void pciauto_setup_device(struct pci_controller *hose,
29 pci_dev_t dev, int bars_num,
30 struct pci_region *mem,
31 struct pci_region *prefetch,
32 struct pci_region *io)
38 #ifndef CONFIG_PCI_ENUM_ONLY
42 struct pci_region *bar_res;
47 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
48 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
50 for (bar = PCI_BASE_ADDRESS_0;
51 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
52 /* Tickle the BAR and get the response */
53 #ifndef CONFIG_PCI_ENUM_ONLY
54 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
56 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
58 /* If BAR is not implemented go to the next BAR */
62 #ifndef CONFIG_PCI_ENUM_ONLY
66 /* Check the BAR type and set our address mask */
67 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
68 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
70 #ifndef CONFIG_PCI_ENUM_ONLY
74 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
75 bar_nr, (unsigned long long)bar_size);
77 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
78 PCI_BASE_ADDRESS_MEM_TYPE_64) {
79 u32 bar_response_upper;
82 #ifndef CONFIG_PCI_ENUM_ONLY
83 pci_hose_write_config_dword(hose, dev, bar + 4,
86 pci_hose_read_config_dword(hose, dev, bar + 4,
89 bar64 = ((u64)bar_response_upper << 32) | bar_response;
91 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
92 #ifndef CONFIG_PCI_ENUM_ONLY
96 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
98 #ifndef CONFIG_PCI_ENUM_ONLY
99 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
104 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
105 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
106 (unsigned long long)bar_size);
110 #ifndef CONFIG_PCI_ENUM_ONLY
111 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
112 /* Write it out and update our limit */
113 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
117 #ifdef CONFIG_SYS_PCI_64BIT
118 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
121 * If we are a 64-bit decoder then increment to the
122 * upper 32 bits of the bar and force it to locate
123 * in the lower 4GB of memory.
125 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
131 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
132 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
139 #ifndef CONFIG_PCI_ENUM_ONLY
140 /* Configure the expansion ROM address */
141 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
143 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
144 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
145 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
146 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
147 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
149 bar_size = -(bar_response & ~1);
150 debug("PCI Autoconfig: ROM, size=%#x, ",
151 (unsigned int)bar_size);
152 if (pciauto_region_allocate(mem, bar_size,
154 pci_hose_write_config_dword(hose, dev, rom_addr,
157 cmdstat |= PCI_COMMAND_MEMORY;
163 /* PCI_COMMAND_IO must be set for VGA device */
164 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
165 if (class == PCI_CLASS_DISPLAY_VGA)
166 cmdstat |= PCI_COMMAND_IO;
168 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
169 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
170 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
171 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
174 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
175 pci_dev_t dev, int sub_bus)
177 struct pci_region *pci_mem;
178 struct pci_region *pci_prefetch;
179 struct pci_region *pci_io;
180 u16 cmdstat, prefechable_64;
182 pci_mem = hose->pci_mem;
183 pci_prefetch = hose->pci_prefetch;
184 pci_io = hose->pci_io;
186 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
187 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
189 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
191 /* Configure bus number registers */
192 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
193 PCI_BUS(dev) - hose->first_busno);
194 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
195 sub_bus - hose->first_busno);
196 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
199 /* Round memory allocator to 1MB boundary */
200 pciauto_region_align(pci_mem, 0x100000);
202 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
203 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
204 (pci_mem->bus_lower & 0xfff00000) >> 16);
206 cmdstat |= PCI_COMMAND_MEMORY;
210 /* Round memory allocator to 1MB boundary */
211 pciauto_region_align(pci_prefetch, 0x100000);
213 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
214 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
215 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
216 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
217 #ifdef CONFIG_SYS_PCI_64BIT
218 pci_hose_write_config_dword(hose, dev,
219 PCI_PREF_BASE_UPPER32,
220 pci_prefetch->bus_lower >> 32);
222 pci_hose_write_config_dword(hose, dev,
223 PCI_PREF_BASE_UPPER32,
227 cmdstat |= PCI_COMMAND_MEMORY;
229 /* We don't support prefetchable memory for now, so disable */
230 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
231 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
232 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
233 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
234 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
239 /* Round I/O allocator to 4KB boundary */
240 pciauto_region_align(pci_io, 0x1000);
242 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
243 (pci_io->bus_lower & 0x0000f000) >> 8);
244 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
245 (pci_io->bus_lower & 0xffff0000) >> 16);
247 cmdstat |= PCI_COMMAND_IO;
250 /* Enable memory and I/O accesses, enable bus master */
251 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
252 cmdstat | PCI_COMMAND_MASTER);
255 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
256 pci_dev_t dev, int sub_bus)
258 struct pci_region *pci_mem;
259 struct pci_region *pci_prefetch;
260 struct pci_region *pci_io;
262 pci_mem = hose->pci_mem;
263 pci_prefetch = hose->pci_prefetch;
264 pci_io = hose->pci_io;
266 /* Configure bus number registers */
267 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
268 sub_bus - hose->first_busno);
271 /* Round memory allocator to 1MB boundary */
272 pciauto_region_align(pci_mem, 0x100000);
274 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
275 (pci_mem->bus_lower - 1) >> 16);
281 pci_hose_read_config_word(hose, dev,
282 PCI_PREF_MEMORY_LIMIT,
284 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
286 /* Round memory allocator to 1MB boundary */
287 pciauto_region_align(pci_prefetch, 0x100000);
289 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
290 (pci_prefetch->bus_lower - 1) >> 16);
291 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
292 #ifdef CONFIG_SYS_PCI_64BIT
293 pci_hose_write_config_dword(hose, dev,
294 PCI_PREF_LIMIT_UPPER32,
295 (pci_prefetch->bus_lower - 1) >> 32);
297 pci_hose_write_config_dword(hose, dev,
298 PCI_PREF_LIMIT_UPPER32,
304 /* Round I/O allocator to 4KB boundary */
305 pciauto_region_align(pci_io, 0x1000);
307 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
308 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
309 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
310 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
316 * HJF: Changed this to return int. I think this is required
317 * to get the correct result when scanning bridges
319 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
321 struct pci_region *pci_mem;
322 struct pci_region *pci_prefetch;
323 struct pci_region *pci_io;
324 unsigned int sub_bus = PCI_BUS(dev);
325 unsigned short class;
328 pci_mem = hose->pci_mem;
329 pci_prefetch = hose->pci_prefetch;
330 pci_io = hose->pci_io;
332 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
335 case PCI_CLASS_BRIDGE_PCI:
336 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
339 pciauto_setup_device(hose, dev, 2, pci_mem,
340 pci_prefetch, pci_io);
342 /* Passing in current_busno allows for sibling P2P bridges */
343 hose->current_busno++;
344 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
346 * need to figure out if this is a subordinate bridge on the bus
347 * to be able to properly set the pri/sec/sub bridge registers.
349 n = pci_hose_scan_bus(hose, hose->current_busno);
351 /* figure out the deepest we've gone for this leg */
352 sub_bus = max((unsigned int)n, sub_bus);
353 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
355 sub_bus = hose->current_busno;
358 case PCI_CLASS_BRIDGE_CARDBUS:
360 * just do a minimal setup of the bridge,
361 * let the OS take care of the rest
363 pciauto_setup_device(hose, dev, 0, pci_mem,
364 pci_prefetch, pci_io);
366 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
369 hose->current_busno++;
372 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
373 case PCI_CLASS_BRIDGE_OTHER:
374 debug("PCI Autoconfig: Skipping bridge device %d\n",
378 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
379 case PCI_CLASS_BRIDGE_OTHER:
381 * The host/PCI bridge 1 seems broken in 8349 - it presents
382 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
383 * device claiming resources io/mem/irq.. we only allow for
384 * the PIMMR window to be allocated (BAR0 - 1MB size)
386 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
387 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
388 hose->pci_prefetch, hose->pci_io);
392 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
393 debug("PCI AutoConfig: Found PowerPC device\n");
396 pciauto_setup_device(hose, dev, 6, pci_mem,
397 pci_prefetch, pci_io);