drivers/pci/pci_auto.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PCI autoconfiguration library
   4  *
   5  * Author: Matt Porter <mporter@mvista.com>
   6  *
   7  * Copyright 2000 MontaVista Software Inc.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <pci.h>
  14
  15 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  16 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  17 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  18 #endif
  19
  20 void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
  21                              struct pci_region *mem,
  22                              struct pci_region *prefetch, struct pci_region *io,
  23                              bool enum_only)
  24 {
  25         u32 bar_response;
  26         pci_size_t bar_size;
  27         u16 cmdstat = 0;
  28         int bar, bar_nr = 0;
  29         u8 header_type;
  30         int rom_addr;
  31         pci_addr_t bar_value;
  32         struct pci_region *bar_res = NULL;
  33         int found_mem64 = 0;
  34         u16 class;
  35
  36         dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
  37         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
  38                         PCI_COMMAND_MASTER;
  39
  40         for (bar = PCI_BASE_ADDRESS_0;
  41              bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  42                 int ret = 0;
  43
  44                 /* Tickle the BAR and get the response */
  45                 if (!enum_only)
  46                         dm_pci_write_config32(dev, bar, 0xffffffff);
  47                 dm_pci_read_config32(dev, bar, &bar_response);
  48
  49                 /* If BAR is not implemented go to the next BAR */
  50                 if (!bar_response)
  51                         continue;
  52
  53                 found_mem64 = 0;
  54
  55                 /* Check the BAR type and set our address mask */
  56                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  57                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
  58                                    & 0xffff) + 1;
  59                         if (!enum_only)
  60                                 bar_res = io;
  61
  62                         debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  63                               bar_nr, (unsigned long long)bar_size);
  64                 } else {
  65                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  66                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
  67                                 u32 bar_response_upper;
  68                                 u64 bar64;
  69
  70                                 if (!enum_only) {
  71                                         dm_pci_write_config32(dev, bar + 4,
  72                                                               0xffffffff);
  73                                 }
  74                                 dm_pci_read_config32(dev, bar + 4,
  75                                                      &bar_response_upper);
  76
  77                                 bar64 = ((u64)bar_response_upper << 32) |
  78                                                 bar_response;
  79
  80                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
  81                                                 + 1;
  82                                 if (!enum_only)
  83                                         found_mem64 = 1;
  84                         } else {
  85                                 bar_size = (u32)(~(bar_response &
  86                                                 PCI_BASE_ADDRESS_MEM_MASK) + 1);
  87                         }
  88                         if (!enum_only) {
  89                                 if (prefetch && (bar_response &
  90                                             PCI_BASE_ADDRESS_MEM_PREFETCH)) {
  91                                         bar_res = prefetch;
  92                                 } else {
  93                                         bar_res = mem;
  94                                 }
  95                         }
  96
  97                         debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
  98                               bar_nr, bar_res == prefetch ? "Prf" : "Mem",
  99                               (unsigned long long)bar_size);
 100                 }
 101
 102                 if (!enum_only) {
 103                         ret = pciauto_region_allocate(bar_res, bar_size,
 104                                                       &bar_value, found_mem64);
 105                         if (ret)
 106                                 printf("PCI: Failed autoconfig bar %x\n", bar);
 107                 }
 108                 if (!enum_only && !ret) {
 109                         /* Write it out and update our limit */
 110                         dm_pci_write_config32(dev, bar, (u32)bar_value);
 111
 112                         if (found_mem64) {
 113                                 bar += 4;
 114 #ifdef CONFIG_SYS_PCI_64BIT
 115                                 dm_pci_write_config32(dev, bar,
 116                                                       (u32)(bar_value >> 32));
 117 #else
 118                                 /*
 119                                  * If we are a 64-bit decoder then increment to
 120                                  * the upper 32 bits of the bar and force it to
 121                                  * locate in the lower 4GB of memory.
 122                                  */
 123                                 dm_pci_write_config32(dev, bar, 0x00000000);
 124 #endif
 125                         }
 126                 }
 127
 128                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 129                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 130
 131                 debug("\n");
 132
 133                 bar_nr++;
 134         }
 135
 136         if (!enum_only) {
 137                 /* Configure the expansion ROM address */
 138                 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
 139                 header_type &= 0x7f;
 140                 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
 141                         rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
 142                                 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
 143                         dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
 144                         dm_pci_read_config32(dev, rom_addr, &bar_response);
 145                         if (bar_response) {
 146                                 bar_size = -(bar_response & ~1);
 147                                 debug("PCI Autoconfig: ROM, size=%#x, ",
 148                                       (unsigned int)bar_size);
 149                                 if (pciauto_region_allocate(mem, bar_size,
 150                                                             &bar_value,
 151                                                             false) == 0) {
 152                                         dm_pci_write_config32(dev, rom_addr,
 153                                                               bar_value);
 154                                 }
 155                                 cmdstat |= PCI_COMMAND_MEMORY;
 156                                 debug("\n");
 157                         }
 158                 }
 159         }
 160
 161         /* PCI_COMMAND_IO must be set for VGA device */
 162         dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
 163         if (class == PCI_CLASS_DISPLAY_VGA)
 164                 cmdstat |= PCI_COMMAND_IO;
 165
 166         dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
 167         dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
 168                              CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 169         dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
 170 }
 171
 172 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
 173 {
 174         struct pci_region *pci_mem;
 175         struct pci_region *pci_prefetch;
 176         struct pci_region *pci_io;
 177         u16 cmdstat, prefechable_64;
 178         struct udevice *ctlr = pci_get_controller(dev);
 179         struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 180
 181         pci_mem = ctlr_hose->pci_mem;
 182         pci_prefetch = ctlr_hose->pci_prefetch;
 183         pci_io = ctlr_hose->pci_io;
 184
 185         dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
 186         dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
 187         prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 188
 189         /* Configure bus number registers */
 190         dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
 191                              PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq);
 192         dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq);
 193         dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
 194
 195         if (pci_mem) {
 196                 /* Round memory allocator to 1MB boundary */
 197                 pciauto_region_align(pci_mem, 0x100000);
 198
 199                 /*
 200                  * Set up memory and I/O filter limits, assume 32-bit
 201                  * I/O space
 202                  */
 203                 dm_pci_write_config16(dev, PCI_MEMORY_BASE,
 204                                       (pci_mem->bus_lower & 0xfff00000) >> 16);
 205
 206                 cmdstat |= PCI_COMMAND_MEMORY;
 207         }
 208
 209         if (pci_prefetch) {
 210                 /* Round memory allocator to 1MB boundary */
 211                 pciauto_region_align(pci_prefetch, 0x100000);
 212
 213                 /*
 214                  * Set up memory and I/O filter limits, assume 32-bit
 215                  * I/O space
 216                  */
 217                 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
 218                                 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 219                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 220 #ifdef CONFIG_SYS_PCI_64BIT
 221                         dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
 222                                               pci_prefetch->bus_lower >> 32);
 223 #else
 224                         dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
 225 #endif
 226
 227                 cmdstat |= PCI_COMMAND_MEMORY;
 228         } else {
 229                 /* We don't support prefetchable memory for now, so disable */
 230                 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
 231                 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 232                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
 233                         dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
 234                         dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 235                 }
 236         }
 237
 238         if (pci_io) {
 239                 /* Round I/O allocator to 4KB boundary */
 240                 pciauto_region_align(pci_io, 0x1000);
 241
 242                 dm_pci_write_config8(dev, PCI_IO_BASE,
 243                                      (pci_io->bus_lower & 0x0000f000) >> 8);
 244                 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
 245                                       (pci_io->bus_lower & 0xffff0000) >> 16);
 246
 247                 cmdstat |= PCI_COMMAND_IO;
 248         }
 249
 250         /* Enable memory and I/O accesses, enable bus master */
 251         dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
 252 }
 253
 254 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
 255 {
 256         struct pci_region *pci_mem;
 257         struct pci_region *pci_prefetch;
 258         struct pci_region *pci_io;
 259         struct udevice *ctlr = pci_get_controller(dev);
 260         struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 261
 262         pci_mem = ctlr_hose->pci_mem;
 263         pci_prefetch = ctlr_hose->pci_prefetch;
 264         pci_io = ctlr_hose->pci_io;
 265
 266         /* Configure bus number registers */
 267         dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq);
 268
 269         if (pci_mem) {
 270                 /* Round memory allocator to 1MB boundary */
 271                 pciauto_region_align(pci_mem, 0x100000);
 272
 273                 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
 274                                       (pci_mem->bus_lower - 1) >> 16);
 275         }
 276
 277         if (pci_prefetch) {
 278                 u16 prefechable_64;
 279
 280                 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
 281                                      &prefechable_64);
 282                 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 283
 284                 /* Round memory allocator to 1MB boundary */
 285                 pciauto_region_align(pci_prefetch, 0x100000);
 286
 287                 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
 288                                       (pci_prefetch->bus_lower - 1) >> 16);
 289                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 290 #ifdef CONFIG_SYS_PCI_64BIT
 291                         dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
 292                                         (pci_prefetch->bus_lower - 1) >> 32);
 293 #else
 294                         dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 295 #endif
 296         }
 297
 298         if (pci_io) {
 299                 /* Round I/O allocator to 4KB boundary */
 300                 pciauto_region_align(pci_io, 0x1000);
 301
 302                 dm_pci_write_config8(dev, PCI_IO_LIMIT,
 303                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 304                 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
 305                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 306         }
 307 }
 308
 309 /*
 310  * HJF: Changed this to return int. I think this is required
 311  * to get the correct result when scanning bridges
 312  */
 313 int dm_pciauto_config_device(struct udevice *dev)
 314 {
 315         struct pci_region *pci_mem;
 316         struct pci_region *pci_prefetch;
 317         struct pci_region *pci_io;
 318         unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
 319         unsigned short class;
 320         bool enum_only = false;
 321         struct udevice *ctlr = pci_get_controller(dev);
 322         struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 323         int n;
 324
 325 #ifdef CONFIG_PCI_ENUM_ONLY
 326         enum_only = true;
 327 #endif
 328
 329         pci_mem = ctlr_hose->pci_mem;
 330         pci_prefetch = ctlr_hose->pci_prefetch;
 331         pci_io = ctlr_hose->pci_io;
 332
 333         dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
 334
 335         switch (class) {
 336         case PCI_CLASS_BRIDGE_PCI:
 337                 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
 338                       PCI_DEV(dm_pci_get_bdf(dev)));
 339
 340                 dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
 341                                         enum_only);
 342
 343                 n = dm_pci_hose_probe_bus(dev);
 344                 if (n < 0)
 345                         return n;
 346                 sub_bus = (unsigned int)n;
 347                 break;
 348
 349         case PCI_CLASS_BRIDGE_CARDBUS:
 350                 /*
 351                  * just do a minimal setup of the bridge,
 352                  * let the OS take care of the rest
 353                  */
 354                 dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
 355                                         enum_only);
 356
 357                 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 358                       PCI_DEV(dm_pci_get_bdf(dev)));
 359
 360                 break;
 361
 362 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 363         case PCI_CLASS_BRIDGE_OTHER:
 364                 debug("PCI Autoconfig: Skipping bridge device %d\n",
 365                       PCI_DEV(dm_pci_get_bdf(dev)));
 366                 break;
 367 #endif
 368 #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
 369                 !defined(CONFIG_TARGET_CADDY2)
 370         case PCI_CLASS_BRIDGE_OTHER:
 371                 /*
 372                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 373                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 374                  * device claiming resources io/mem/irq.. we only allow for
 375                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 376                  */
 377                 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
 378                 dm_pciauto_setup_device(dev, 0, hose->pci_mem,
 379                                         hose->pci_prefetch, hose->pci_io,
 380                                         enum_only);
 381                 break;
 382 #endif
 383
 384         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 385                 debug("PCI AutoConfig: Found PowerPC device\n");
 386                 /* fall through */
 387
 388         default:
 389                 dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
 390                                         enum_only);
 391                 break;
 392         }
 393
 394         return sub_bus;
 395 }