2 * arch/powerpc/kernel/pci_auto.c
4 * PCI autoconfiguration library
6 * Author: Matt Porter <mporter@mvista.com>
8 * Copyright 2000 MontaVista Software Inc.
10 * SPDX-License-Identifier: GPL-2.0+
19 #define DEBUGF(x...) printf(x)
24 #define PCIAUTO_IDE_MODE_MASK 0x05
26 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
27 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
28 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
35 void pciauto_region_init(struct pci_region *res)
38 * Avoid allocating PCI resources from address 0 -- this is illegal
39 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
40 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
42 res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
45 void pciauto_region_align(struct pci_region *res, pci_size_t size)
47 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
50 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
56 DEBUGF("No resource");
60 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
62 if (addr - res->bus_start + size > res->size) {
63 DEBUGF("No room in resource");
67 res->bus_lower = addr + size;
69 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
75 *bar = (pci_addr_t)-1;
83 void pciauto_setup_device(struct pci_controller *hose,
84 pci_dev_t dev, int bars_num,
85 struct pci_region *mem,
86 struct pci_region *prefetch,
87 struct pci_region *io)
93 #ifndef CONFIG_PCI_ENUM_ONLY
95 struct pci_region *bar_res;
99 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
100 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
102 for (bar = PCI_BASE_ADDRESS_0;
103 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
104 /* Tickle the BAR and get the response */
105 #ifndef CONFIG_PCI_ENUM_ONLY
106 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
108 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
110 /* If BAR is not implemented go to the next BAR */
114 #ifndef CONFIG_PCI_ENUM_ONLY
118 /* Check the BAR type and set our address mask */
119 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
120 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
122 #ifndef CONFIG_PCI_ENUM_ONLY
126 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
128 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
129 PCI_BASE_ADDRESS_MEM_TYPE_64) {
130 u32 bar_response_upper;
133 #ifndef CONFIG_PCI_ENUM_ONLY
134 pci_hose_write_config_dword(hose, dev, bar + 4,
137 pci_hose_read_config_dword(hose, dev, bar + 4,
138 &bar_response_upper);
140 bar64 = ((u64)bar_response_upper << 32) | bar_response;
142 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
143 #ifndef CONFIG_PCI_ENUM_ONLY
147 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
149 #ifndef CONFIG_PCI_ENUM_ONLY
150 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
156 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
159 #ifndef CONFIG_PCI_ENUM_ONLY
160 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
161 /* Write it out and update our limit */
162 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
166 #ifdef CONFIG_SYS_PCI_64BIT
167 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
170 * If we are a 64-bit decoder then increment to the
171 * upper 32 bits of the bar and force it to locate
172 * in the lower 4GB of memory.
174 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
180 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
181 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
188 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
189 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
190 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
191 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
194 int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev)
196 pci_addr_t bar_value;
201 pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe);
202 pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response);
206 bar_size = -(bar_response & ~1);
207 DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
208 if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) {
209 pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
213 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
214 cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
215 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
220 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
221 pci_dev_t dev, int sub_bus)
223 struct pci_region *pci_mem = hose->pci_mem;
224 struct pci_region *pci_prefetch = hose->pci_prefetch;
225 struct pci_region *pci_io = hose->pci_io;
228 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
230 /* Configure bus number registers */
231 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
232 PCI_BUS(dev) - hose->first_busno);
233 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
234 sub_bus - hose->first_busno);
235 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
238 /* Round memory allocator to 1MB boundary */
239 pciauto_region_align(pci_mem, 0x100000);
241 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
242 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
243 (pci_mem->bus_lower & 0xfff00000) >> 16);
245 cmdstat |= PCI_COMMAND_MEMORY;
249 /* Round memory allocator to 1MB boundary */
250 pciauto_region_align(pci_prefetch, 0x100000);
252 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
253 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
254 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
256 cmdstat |= PCI_COMMAND_MEMORY;
258 /* We don't support prefetchable memory for now, so disable */
259 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
260 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
264 /* Round I/O allocator to 4KB boundary */
265 pciauto_region_align(pci_io, 0x1000);
267 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
268 (pci_io->bus_lower & 0x0000f000) >> 8);
269 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
270 (pci_io->bus_lower & 0xffff0000) >> 16);
272 cmdstat |= PCI_COMMAND_IO;
275 /* Enable memory and I/O accesses, enable bus master */
276 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
277 cmdstat | PCI_COMMAND_MASTER);
280 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
281 pci_dev_t dev, int sub_bus)
283 struct pci_region *pci_mem = hose->pci_mem;
284 struct pci_region *pci_prefetch = hose->pci_prefetch;
285 struct pci_region *pci_io = hose->pci_io;
287 /* Configure bus number registers */
288 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
289 sub_bus - hose->first_busno);
292 /* Round memory allocator to 1MB boundary */
293 pciauto_region_align(pci_mem, 0x100000);
295 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
296 (pci_mem->bus_lower - 1) >> 16);
300 /* Round memory allocator to 1MB boundary */
301 pciauto_region_align(pci_prefetch, 0x100000);
303 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
304 (pci_prefetch->bus_lower - 1) >> 16);
308 /* Round I/O allocator to 4KB boundary */
309 pciauto_region_align(pci_io, 0x1000);
311 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
312 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
313 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
314 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
322 void pciauto_config_init(struct pci_controller *hose)
326 hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
328 for (i = 0; i < hose->region_count; i++) {
329 switch(hose->regions[i].flags) {
332 hose->pci_io->size < hose->regions[i].size)
333 hose->pci_io = hose->regions + i;
336 if (!hose->pci_mem ||
337 hose->pci_mem->size < hose->regions[i].size)
338 hose->pci_mem = hose->regions + i;
340 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
341 if (!hose->pci_prefetch ||
342 hose->pci_prefetch->size < hose->regions[i].size)
343 hose->pci_prefetch = hose->regions + i;
350 pciauto_region_init(hose->pci_mem);
352 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
353 "\t\tPhysical Memory [%llx-%llxx]\n",
354 (u64)hose->pci_mem->bus_start,
355 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
356 (u64)hose->pci_mem->phys_start,
357 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
360 if (hose->pci_prefetch) {
361 pciauto_region_init(hose->pci_prefetch);
363 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
364 "\t\tPhysical Memory [%llx-%llx]\n",
365 (u64)hose->pci_prefetch->bus_start,
366 (u64)(hose->pci_prefetch->bus_start +
367 hose->pci_prefetch->size - 1),
368 (u64)hose->pci_prefetch->phys_start,
369 (u64)(hose->pci_prefetch->phys_start +
370 hose->pci_prefetch->size - 1));
374 pciauto_region_init(hose->pci_io);
376 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
377 "\t\tPhysical Memory: [%llx-%llx]\n",
378 (u64)hose->pci_io->bus_start,
379 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
380 (u64)hose->pci_io->phys_start,
381 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
387 * HJF: Changed this to return int. I think this is required
388 * to get the correct result when scanning bridges
390 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
392 unsigned int sub_bus = PCI_BUS(dev);
393 unsigned short class;
394 unsigned char prg_iface;
397 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
400 case PCI_CLASS_BRIDGE_PCI:
401 hose->current_busno++;
402 pciauto_setup_device(hose, dev, 2, hose->pci_mem,
403 hose->pci_prefetch, hose->pci_io);
405 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
407 /* Passing in current_busno allows for sibling P2P bridges */
408 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
410 * need to figure out if this is a subordinate bridge on the bus
411 * to be able to properly set the pri/sec/sub bridge registers.
413 n = pci_hose_scan_bus(hose, hose->current_busno);
415 /* figure out the deepest we've gone for this leg */
416 sub_bus = max((unsigned int)n, sub_bus);
417 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
419 sub_bus = hose->current_busno;
422 case PCI_CLASS_STORAGE_IDE:
423 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
424 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
425 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
429 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
430 hose->pci_prefetch, hose->pci_io);
433 case PCI_CLASS_BRIDGE_CARDBUS:
435 * just do a minimal setup of the bridge,
436 * let the OS take care of the rest
438 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
439 hose->pci_prefetch, hose->pci_io);
441 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
444 hose->current_busno++;
447 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
448 case PCI_CLASS_BRIDGE_OTHER:
449 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
453 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
454 case PCI_CLASS_BRIDGE_OTHER:
456 * The host/PCI bridge 1 seems broken in 8349 - it presents
457 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
458 * device claiming resources io/mem/irq.. we only allow for
459 * the PIMMR window to be allocated (BAR0 - 1MB size)
461 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
462 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
463 hose->pci_prefetch, hose->pci_io);
467 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
468 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
471 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
472 hose->pci_prefetch, hose->pci_io);