1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI autoconfiguration library
5 * Author: Matt Porter <mporter@mvista.com>
7 * Copyright 2000 MontaVista Software Inc.
16 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
17 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
18 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
21 void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
22 struct pci_region *mem,
23 struct pci_region *prefetch, struct pci_region *io,
33 struct pci_region *bar_res = NULL;
37 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
38 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
41 for (bar = PCI_BASE_ADDRESS_0;
42 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
45 /* Tickle the BAR and get the response */
47 dm_pci_write_config32(dev, bar, 0xffffffff);
48 dm_pci_read_config32(dev, bar, &bar_response);
50 /* If BAR is not implemented go to the next BAR */
56 /* Check the BAR type and set our address mask */
57 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
58 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
63 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
64 bar_nr, (unsigned long long)bar_size);
66 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
67 PCI_BASE_ADDRESS_MEM_TYPE_64) {
68 u32 bar_response_upper;
72 dm_pci_write_config32(dev, bar + 4,
75 dm_pci_read_config32(dev, bar + 4,
78 bar64 = ((u64)bar_response_upper << 32) |
81 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
86 bar_size = (u32)(~(bar_response &
87 PCI_BASE_ADDRESS_MEM_MASK) + 1);
90 if (prefetch && (bar_response &
91 PCI_BASE_ADDRESS_MEM_PREFETCH)) {
98 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
99 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
100 (unsigned long long)bar_size);
104 ret = pciauto_region_allocate(bar_res, bar_size,
105 &bar_value, found_mem64);
107 printf("PCI: Failed autoconfig bar %x\n", bar);
109 if (!enum_only && !ret) {
110 /* Write it out and update our limit */
111 dm_pci_write_config32(dev, bar, (u32)bar_value);
115 #ifdef CONFIG_SYS_PCI_64BIT
116 dm_pci_write_config32(dev, bar,
117 (u32)(bar_value >> 32));
120 * If we are a 64-bit decoder then increment to
121 * the upper 32 bits of the bar and force it to
122 * locate in the lower 4GB of memory.
124 dm_pci_write_config32(dev, bar, 0x00000000);
129 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
130 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
138 /* Configure the expansion ROM address */
139 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
141 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
142 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
143 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
144 dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
145 dm_pci_read_config32(dev, rom_addr, &bar_response);
147 bar_size = -(bar_response & ~1);
148 debug("PCI Autoconfig: ROM, size=%#x, ",
149 (unsigned int)bar_size);
150 if (pciauto_region_allocate(mem, bar_size,
153 dm_pci_write_config32(dev, rom_addr,
156 cmdstat |= PCI_COMMAND_MEMORY;
162 /* PCI_COMMAND_IO must be set for VGA device */
163 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
164 if (class == PCI_CLASS_DISPLAY_VGA)
165 cmdstat |= PCI_COMMAND_IO;
167 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
168 dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
169 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
170 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
173 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
175 struct pci_region *pci_mem;
176 struct pci_region *pci_prefetch;
177 struct pci_region *pci_io;
178 u16 cmdstat, prefechable_64;
179 struct udevice *ctlr = pci_get_controller(dev);
180 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
182 pci_mem = ctlr_hose->pci_mem;
183 pci_prefetch = ctlr_hose->pci_prefetch;
184 pci_io = ctlr_hose->pci_io;
186 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
187 dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
188 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
190 /* Configure bus number registers */
191 dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
192 PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq);
193 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq);
194 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
197 /* Round memory allocator to 1MB boundary */
198 pciauto_region_align(pci_mem, 0x100000);
201 * Set up memory and I/O filter limits, assume 32-bit
204 dm_pci_write_config16(dev, PCI_MEMORY_BASE,
205 (pci_mem->bus_lower & 0xfff00000) >> 16);
207 cmdstat |= PCI_COMMAND_MEMORY;
211 /* Round memory allocator to 1MB boundary */
212 pciauto_region_align(pci_prefetch, 0x100000);
215 * Set up memory and I/O filter limits, assume 32-bit
218 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
219 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
220 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
221 #ifdef CONFIG_SYS_PCI_64BIT
222 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
223 pci_prefetch->bus_lower >> 32);
225 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
228 cmdstat |= PCI_COMMAND_MEMORY;
230 /* We don't support prefetchable memory for now, so disable */
231 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
232 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
233 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
234 dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
235 dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
240 /* Round I/O allocator to 4KB boundary */
241 pciauto_region_align(pci_io, 0x1000);
243 dm_pci_write_config8(dev, PCI_IO_BASE,
244 (pci_io->bus_lower & 0x0000f000) >> 8);
245 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
246 (pci_io->bus_lower & 0xffff0000) >> 16);
248 cmdstat |= PCI_COMMAND_IO;
251 /* Enable memory and I/O accesses, enable bus master */
252 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
255 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
257 struct pci_region *pci_mem;
258 struct pci_region *pci_prefetch;
259 struct pci_region *pci_io;
260 struct udevice *ctlr = pci_get_controller(dev);
261 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
263 pci_mem = ctlr_hose->pci_mem;
264 pci_prefetch = ctlr_hose->pci_prefetch;
265 pci_io = ctlr_hose->pci_io;
267 /* Configure bus number registers */
268 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq);
271 /* Round memory allocator to 1MB boundary */
272 pciauto_region_align(pci_mem, 0x100000);
274 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
275 (pci_mem->bus_lower - 1) >> 16);
281 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
283 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
285 /* Round memory allocator to 1MB boundary */
286 pciauto_region_align(pci_prefetch, 0x100000);
288 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
289 (pci_prefetch->bus_lower - 1) >> 16);
290 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
291 #ifdef CONFIG_SYS_PCI_64BIT
292 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
293 (pci_prefetch->bus_lower - 1) >> 32);
295 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
300 /* Round I/O allocator to 4KB boundary */
301 pciauto_region_align(pci_io, 0x1000);
303 dm_pci_write_config8(dev, PCI_IO_LIMIT,
304 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
305 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
306 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
311 * HJF: Changed this to return int. I think this is required
312 * to get the correct result when scanning bridges
314 int dm_pciauto_config_device(struct udevice *dev)
316 struct pci_region *pci_mem;
317 struct pci_region *pci_prefetch;
318 struct pci_region *pci_io;
319 unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
320 unsigned short class;
321 bool enum_only = false;
322 struct udevice *ctlr = pci_get_controller(dev);
323 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
326 #ifdef CONFIG_PCI_ENUM_ONLY
330 pci_mem = ctlr_hose->pci_mem;
331 pci_prefetch = ctlr_hose->pci_prefetch;
332 pci_io = ctlr_hose->pci_io;
334 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
337 case PCI_CLASS_BRIDGE_PCI:
338 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
339 PCI_DEV(dm_pci_get_bdf(dev)));
341 dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
344 n = dm_pci_hose_probe_bus(dev);
347 sub_bus = (unsigned int)n;
350 case PCI_CLASS_BRIDGE_CARDBUS:
352 * just do a minimal setup of the bridge,
353 * let the OS take care of the rest
355 dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
358 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
359 PCI_DEV(dm_pci_get_bdf(dev)));
363 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
364 case PCI_CLASS_BRIDGE_OTHER:
365 debug("PCI Autoconfig: Skipping bridge device %d\n",
366 PCI_DEV(dm_pci_get_bdf(dev)));
369 #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
370 !defined(CONFIG_TARGET_CADDY2)
371 case PCI_CLASS_BRIDGE_OTHER:
373 * The host/PCI bridge 1 seems broken in 8349 - it presents
374 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
375 * device claiming resources io/mem/irq.. we only allow for
376 * the PIMMR window to be allocated (BAR0 - 1MB size)
378 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
379 dm_pciauto_setup_device(dev, 0, hose->pci_mem,
380 hose->pci_prefetch, hose->pci_io,
385 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
386 debug("PCI AutoConfig: Found PowerPC device\n");
390 dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,