1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
6 * (C) Copyright 2002, 2003
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
14 * and change pci-uclass.c.
22 #include <asm/processor.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define PCI_HOSE_OP(rw, size, type) \
29 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
31 int offset, type value) \
33 return hose->rw##_##size(hose, dev, offset, value); \
36 PCI_HOSE_OP(read, byte, u8 *)
37 PCI_HOSE_OP(read, word, u16 *)
38 PCI_HOSE_OP(read, dword, u32 *)
39 PCI_HOSE_OP(write, byte, u8)
40 PCI_HOSE_OP(write, word, u16)
41 PCI_HOSE_OP(write, dword, u32)
43 #define PCI_OP(rw, size, type, error_code) \
44 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
46 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
54 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
57 PCI_OP(read, byte, u8 *, *value = 0xff)
58 PCI_OP(read, word, u16 *, *value = 0xffff)
59 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
60 PCI_OP(write, byte, u8, )
61 PCI_OP(write, word, u16, )
62 PCI_OP(write, dword, u32, )
64 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
65 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
67 int offset, type val) \
71 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
76 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
81 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
82 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
84 int offset, type val) \
86 u32 val32, mask, ldata, shift; \
88 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
91 shift = ((offset & (int)off_mask) * 8); \
92 ldata = (((unsigned long)val) & val_mask) << shift; \
93 mask = val_mask << shift; \
94 val32 = (val32 & ~mask) | ldata; \
96 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
102 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
103 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
104 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
105 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
111 static struct pci_controller* hose_head;
113 struct pci_controller *pci_get_hose_head(void)
121 void pci_register_hose(struct pci_controller* hose)
123 struct pci_controller **phose = &hose_head;
126 phose = &(*phose)->next;
133 struct pci_controller *pci_bus_to_hose(int bus)
135 struct pci_controller *hose;
137 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
138 if (bus >= hose->first_busno && bus <= hose->last_busno)
142 printf("pci_bus_to_hose() failed\n");
146 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
148 struct pci_controller *hose;
150 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
151 if (hose->cfg_addr == cfg_addr)
158 int pci_last_busno(void)
160 struct pci_controller *hose = pci_get_hose_head();
168 return hose->last_busno;
171 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
173 struct pci_controller * hose;
177 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
178 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
179 bdf = pci_hose_find_devices(hose, bus, ids, &index);
188 static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev,
189 ulong io, pci_addr_t mem, ulong command)
192 unsigned int old_command;
193 pci_addr_t bar_value;
196 int bar, found_mem64;
198 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
201 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
203 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
204 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
205 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
212 /* Check the BAR type and set our address mask */
213 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
214 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
215 /* round up region base address to a multiple of size */
216 io = ((io - 1) | (bar_size - 1)) + 1;
218 /* compute new region base address */
221 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
222 PCI_BASE_ADDRESS_MEM_TYPE_64) {
223 u32 bar_response_upper;
225 pci_hose_write_config_dword(hose, dev, bar + 4,
227 pci_hose_read_config_dword(hose, dev, bar + 4,
228 &bar_response_upper);
230 bar64 = ((u64)bar_response_upper << 32) | bar_response;
232 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
235 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
238 /* round up region base address to multiple of size */
239 mem = ((mem - 1) | (bar_size - 1)) + 1;
241 /* compute new region base address */
242 mem = mem + bar_size;
245 /* Write it out and update our limit */
246 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
250 #ifdef CONFIG_SYS_PCI_64BIT
251 pci_hose_write_config_dword(hose, dev, bar,
252 (u32)(bar_value >> 32));
254 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
259 /* Configure Cache Line Size Register */
260 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
262 /* Configure Latency Timer */
263 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
265 /* Disable interrupt line, if device says it wants to use interrupts */
266 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
268 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
269 PCI_INTERRUPT_LINE_DISABLE);
272 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
273 pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
274 (old_command & 0xffff0000) | command);
283 struct pci_config_table *pci_find_config(struct pci_controller *hose,
284 unsigned short class,
291 struct pci_config_table *table;
293 for (table = hose->config_table; table && table->vendor; table++) {
294 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
295 (table->device == PCI_ANY_ID || table->device == device) &&
296 (table->class == PCI_ANY_ID || table->class == class) &&
297 (table->bus == PCI_ANY_ID || table->bus == bus) &&
298 (table->dev == PCI_ANY_ID || table->dev == dev) &&
299 (table->func == PCI_ANY_ID || table->func == func)) {
307 void pci_cfgfunc_config_device(struct pci_controller *hose,
309 struct pci_config_table *entry)
311 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
315 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
316 pci_dev_t dev, struct pci_config_table *entry)
321 * HJF: Changed this to return int. I think this is required
322 * to get the correct result when scanning bridges
324 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
326 #ifdef CONFIG_PCI_SCAN_SHOW
327 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
329 if (dev == PCI_BDF(hose->first_busno, 0, 0))
334 #endif /* CONFIG_PCI_SCAN_SHOW */
336 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
338 unsigned int sub_bus, found_multi = 0;
339 unsigned short vendor, device, class;
340 unsigned char header_type;
341 #ifndef CONFIG_PCI_PNP
342 struct pci_config_table *cfg;
345 #ifdef CONFIG_PCI_SCAN_SHOW
346 static int indent = 0;
351 for (dev = PCI_BDF(bus,0,0);
352 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
353 PCI_MAX_PCI_FUNCTIONS - 1);
354 dev += PCI_BDF(0, 0, 1)) {
356 if (pci_skip_dev(hose, dev))
359 if (PCI_FUNC(dev) && !found_multi)
362 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
364 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
366 if (vendor == 0xffff || vendor == 0x0000)
370 found_multi = header_type & 0x80;
372 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
373 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
375 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
376 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
378 #ifdef CONFIG_PCI_FIXUP_DEV
379 board_pci_fixup_dev(hose, dev, vendor, device, class);
382 #ifdef CONFIG_PCI_SCAN_SHOW
385 /* Print leading space, including bus indentation */
386 printf("%*c", indent + 1, ' ');
388 if (pci_print_dev(hose, dev)) {
389 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
390 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
391 vendor, device, pci_class_str(class >> 8));
395 #ifdef CONFIG_PCI_PNP
396 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
399 cfg = pci_find_config(hose, class, vendor, device,
400 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
402 cfg->config_device(hose, dev, cfg);
403 sub_bus = max(sub_bus,
404 (unsigned int)hose->current_busno);
408 #ifdef CONFIG_PCI_SCAN_SHOW
413 hose->fixup_irq(hose, dev);
419 int pci_hose_scan(struct pci_controller *hose)
421 #if defined(CONFIG_PCI_BOOTDELAY)
425 if (!gd->pcidelay_done) {
426 /* wait "pcidelay" ms (if defined)... */
427 s = env_get("pcidelay");
429 int val = simple_strtoul(s, NULL, 10);
430 for (i = 0; i < val; i++)
433 gd->pcidelay_done = 1;
435 #endif /* CONFIG_PCI_BOOTDELAY */
437 #ifdef CONFIG_PCI_SCAN_SHOW
442 * Start scan at current_busno.
443 * PCIe will start scan at first_busno+1.
445 /* For legacy support, ensure current >= first */
446 if (hose->first_busno > hose->current_busno)
447 hose->current_busno = hose->first_busno;
448 #ifdef CONFIG_PCI_PNP
449 pciauto_config_init(hose);
451 return pci_hose_scan_bus(hose, hose->current_busno);
458 /* allow env to disable pci init/enum */
459 if (env_get("pcidisable") != NULL)
462 /* now call board specific pci_init()... */
466 /* Returns the address of the requested capability structure within the
467 * device's PCI configuration space or 0 in case the device does not
470 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
476 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
478 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
481 pos = pci_find_cap(hose, dev, pos, cap);
486 /* Find the header pointer to the Capabilities*/
487 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
492 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
494 if (!(status & PCI_STATUS_CAP_LIST))
498 case PCI_HEADER_TYPE_NORMAL:
499 case PCI_HEADER_TYPE_BRIDGE:
500 return PCI_CAPABILITY_LIST;
501 case PCI_HEADER_TYPE_CARDBUS:
502 return PCI_CB_CAPABILITY_LIST;
508 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
510 int ttl = PCI_FIND_CAP_TTL;
515 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
516 if (next_pos < CAP_START_POS)
519 pos = (int) next_pos;
520 pci_hose_read_config_byte(hose, dev,
521 pos + PCI_CAP_LIST_ID, &id);
526 pos += PCI_CAP_LIST_NEXT;
532 * pci_find_next_ext_capability - Find an extended capability
534 * Returns the address of the next matching extended capability structure
535 * within the device's PCI configuration space or 0 if the device does
536 * not support it. Some capabilities can occur several times, e.g., the
537 * vendor-specific capability, and this provides a way to find them all.
539 int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
543 int ttl, pos = PCI_CFG_SPACE_SIZE;
545 /* minimum 8 bytes per capability */
546 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
551 pci_hose_read_config_dword(hose, dev, pos, &header);
552 if (header == 0xffffffff || header == 0)
556 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
559 pos = PCI_EXT_CAP_NEXT(header);
560 if (pos < PCI_CFG_SPACE_SIZE)
563 pci_hose_read_config_dword(hose, dev, pos, &header);
564 if (header == 0xffffffff || header == 0)
572 * pci_hose_find_ext_capability - Find an extended capability
574 * Returns the address of the requested extended capability structure
575 * within the device's PCI configuration space or 0 if the device does
578 int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
581 return pci_find_next_ext_capability(hose, dev, 0, cap);