1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
12 #include <dm/device-internal.h>
14 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
15 #include <asm/fsp/fsp_support.h>
17 #include "pci_internal.h"
19 DECLARE_GLOBAL_DATA_PTR;
21 int pci_get_bus(int busnum, struct udevice **busp)
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
27 /* Since buses may not be numbered yet try a little harder with bus 0 */
29 ret = uclass_first_device_err(UCLASS_PCI, busp);
32 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
38 struct udevice *pci_get_controller(struct udevice *dev)
40 while (device_is_on_pci_bus(dev))
46 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
48 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
49 struct udevice *bus = dev->parent;
51 return PCI_ADD_BUS(bus->seq, pplat->devfn);
55 * pci_get_bus_max() - returns the bus number of the last active bus
57 * @return last bus number, or -1 if no active buses
59 static int pci_get_bus_max(void)
65 ret = uclass_get(UCLASS_PCI, &uc);
66 uclass_foreach_dev(bus, uc) {
71 debug("%s: ret=%d\n", __func__, ret);
76 int pci_last_busno(void)
78 return pci_get_bus_max();
81 int pci_get_ff(enum pci_size_t size)
93 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
94 struct udevice **devp)
98 for (device_find_first_child(bus, &dev);
100 device_find_next_child(&dev)) {
101 struct pci_child_platdata *pplat;
103 pplat = dev_get_parent_platdata(dev);
104 if (pplat && pplat->devfn == find_devfn) {
113 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
118 ret = pci_get_bus(PCI_BUS(bdf), &bus);
121 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
124 static int pci_device_matches_ids(struct udevice *dev,
125 struct pci_device_id *ids)
127 struct pci_child_platdata *pplat;
130 pplat = dev_get_parent_platdata(dev);
133 for (i = 0; ids[i].vendor != 0; i++) {
134 if (pplat->vendor == ids[i].vendor &&
135 pplat->device == ids[i].device)
142 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
143 int *indexp, struct udevice **devp)
147 /* Scan all devices on this bus */
148 for (device_find_first_child(bus, &dev);
150 device_find_next_child(&dev)) {
151 if (pci_device_matches_ids(dev, ids) >= 0) {
152 if ((*indexp)-- <= 0) {
162 int pci_find_device_id(struct pci_device_id *ids, int index,
163 struct udevice **devp)
167 /* Scan all known buses */
168 for (uclass_first_device(UCLASS_PCI, &bus);
170 uclass_next_device(&bus)) {
171 if (!pci_bus_find_devices(bus, ids, &index, devp))
179 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
180 unsigned int device, int *indexp,
181 struct udevice **devp)
183 struct pci_child_platdata *pplat;
186 for (device_find_first_child(bus, &dev);
188 device_find_next_child(&dev)) {
189 pplat = dev_get_parent_platdata(dev);
190 if (pplat->vendor == vendor && pplat->device == device) {
201 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
202 struct udevice **devp)
206 /* Scan all known buses */
207 for (uclass_first_device(UCLASS_PCI, &bus);
209 uclass_next_device(&bus)) {
210 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
211 return device_probe(*devp);
218 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
222 /* Scan all known buses */
223 for (pci_find_first_device(&dev);
225 pci_find_next_device(&dev)) {
226 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
228 if (pplat->class == find_class && !index--) {
230 return device_probe(*devp);
238 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
239 unsigned long value, enum pci_size_t size)
241 struct dm_pci_ops *ops;
243 ops = pci_get_ops(bus);
244 if (!ops->write_config)
246 return ops->write_config(bus, bdf, offset, value, size);
249 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
255 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
261 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
264 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
265 enum pci_size_t size)
270 ret = pci_get_bus(PCI_BUS(bdf), &bus);
274 return pci_bus_write_config(bus, bdf, offset, value, size);
277 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
278 enum pci_size_t size)
282 for (bus = dev; device_is_on_pci_bus(bus);)
284 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
288 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
290 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
293 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
295 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
298 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
300 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
303 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
305 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
308 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
310 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
313 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
315 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
318 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
319 unsigned long *valuep, enum pci_size_t size)
321 struct dm_pci_ops *ops;
323 ops = pci_get_ops(bus);
324 if (!ops->read_config)
326 return ops->read_config(bus, bdf, offset, valuep, size);
329 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
330 enum pci_size_t size)
335 ret = pci_get_bus(PCI_BUS(bdf), &bus);
339 return pci_bus_read_config(bus, bdf, offset, valuep, size);
342 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
343 enum pci_size_t size)
347 for (bus = dev; device_is_on_pci_bus(bus);)
349 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
353 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
358 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
366 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
371 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
379 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
384 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
392 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
397 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
405 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
410 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
418 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
423 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
431 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
436 ret = dm_pci_read_config8(dev, offset, &val);
442 return dm_pci_write_config8(dev, offset, val);
445 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
450 ret = dm_pci_read_config16(dev, offset, &val);
456 return dm_pci_write_config16(dev, offset, val);
459 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
464 ret = dm_pci_read_config32(dev, offset, &val);
470 return dm_pci_write_config32(dev, offset, val);
473 static void set_vga_bridge_bits(struct udevice *dev)
475 struct udevice *parent = dev->parent;
478 while (parent->seq != 0) {
479 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
480 bc |= PCI_BRIDGE_CTL_VGA;
481 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
482 parent = parent->parent;
486 int pci_auto_config_devices(struct udevice *bus)
488 struct pci_controller *hose = bus->uclass_priv;
489 struct pci_child_platdata *pplat;
490 unsigned int sub_bus;
495 debug("%s: start\n", __func__);
496 pciauto_config_init(hose);
497 for (ret = device_find_first_child(bus, &dev);
499 ret = device_find_next_child(&dev)) {
500 unsigned int max_bus;
503 debug("%s: device %s\n", __func__, dev->name);
504 ret = dm_pciauto_config_device(dev);
508 sub_bus = max(sub_bus, max_bus);
510 pplat = dev_get_parent_platdata(dev);
511 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
512 set_vga_bridge_bits(dev);
514 debug("%s: done\n", __func__);
519 int pci_generic_mmap_write_config(
521 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
525 enum pci_size_t size)
529 if (addr_f(bus, bdf, offset, &address) < 0)
534 writeb(value, address);
537 writew(value, address);
540 writel(value, address);
547 int pci_generic_mmap_read_config(
549 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
553 enum pci_size_t size)
557 if (addr_f(bus, bdf, offset, &address) < 0) {
558 *valuep = pci_get_ff(size);
564 *valuep = readb(address);
567 *valuep = readw(address);
570 *valuep = readl(address);
577 int dm_pci_hose_probe_bus(struct udevice *bus)
582 debug("%s\n", __func__);
584 sub_bus = pci_get_bus_max() + 1;
585 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
586 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
588 ret = device_probe(bus);
590 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
594 if (sub_bus != bus->seq) {
595 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
596 __func__, bus->name, bus->seq, sub_bus);
599 sub_bus = pci_get_bus_max();
600 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
606 * pci_match_one_device - Tell if a PCI device structure has a matching
607 * PCI device id structure
608 * @id: single PCI device id structure to match
609 * @find: the PCI device id structure to match against
611 * Returns true if the finding pci_device_id structure matched or false if
614 static bool pci_match_one_id(const struct pci_device_id *id,
615 const struct pci_device_id *find)
617 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
618 (id->device == PCI_ANY_ID || id->device == find->device) &&
619 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
620 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
621 !((id->class ^ find->class) & id->class_mask))
628 * pci_find_and_bind_driver() - Find and bind the right PCI driver
630 * This only looks at certain fields in the descriptor.
632 * @parent: Parent bus
633 * @find_id: Specification of the driver to find
634 * @bdf: Bus/device/function addreess - see PCI_BDF()
635 * @devp: Returns a pointer to the device created
636 * @return 0 if OK, -EPERM if the device is not needed before relocation and
637 * therefore was not created, other -ve value on error
639 static int pci_find_and_bind_driver(struct udevice *parent,
640 struct pci_device_id *find_id,
641 pci_dev_t bdf, struct udevice **devp)
643 struct pci_driver_entry *start, *entry;
652 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
653 find_id->vendor, find_id->device);
654 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
655 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
656 for (entry = start; entry != start + n_ents; entry++) {
657 const struct pci_device_id *id;
659 const struct driver *drv;
661 for (id = entry->match;
662 id->vendor || id->subvendor || id->class_mask;
664 if (!pci_match_one_id(id, find_id))
670 * In the pre-relocation phase, we only bind devices
671 * whose driver has the DM_FLAG_PRE_RELOC set, to save
672 * precious memory space as on some platforms as that
673 * space is pretty limited (ie: using Cache As RAM).
675 if (!(gd->flags & GD_FLG_RELOC) &&
676 !(drv->flags & DM_FLAG_PRE_RELOC))
680 * We could pass the descriptor to the driver as
681 * platdata (instead of NULL) and allow its bind()
682 * method to return -ENOENT if it doesn't support this
683 * device. That way we could continue the search to
684 * find another driver. For now this doesn't seem
685 * necesssary, so just bind the first match.
687 ret = device_bind(parent, drv, drv->name, NULL, -1,
691 debug("%s: Match found: %s\n", __func__, drv->name);
692 dev->driver_data = id->driver_data;
698 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
700 * In the pre-relocation phase, we only bind bridge devices to save
701 * precious memory space as on some platforms as that space is pretty
702 * limited (ie: using Cache As RAM).
704 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
707 /* Bind a generic driver so that the device can be used */
708 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
713 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
715 ret = device_bind_driver(parent, drv, str, devp);
717 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
721 debug("%s: No match found: bound generic driver instead\n", __func__);
726 debug("%s: No match found: error %d\n", __func__, ret);
730 int pci_bind_bus_devices(struct udevice *bus)
732 ulong vendor, device;
739 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
740 PCI_MAX_PCI_FUNCTIONS - 1);
741 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
742 bdf += PCI_BDF(0, 0, 1)) {
743 struct pci_child_platdata *pplat;
749 if (PCI_FUNC(bdf) && !found_multi)
751 /* Check only the first access, we don't expect problems */
752 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
753 &header_type, PCI_SIZE_8);
756 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
758 if (vendor == 0xffff || vendor == 0x0000)
762 found_multi = header_type & 0x80;
764 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
765 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
766 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
768 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
772 /* Find this device in the device tree */
773 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
775 /* If nothing in the device tree, bind a device */
776 if (ret == -ENODEV) {
777 struct pci_device_id find_id;
780 memset(&find_id, '\0', sizeof(find_id));
781 find_id.vendor = vendor;
782 find_id.device = device;
783 find_id.class = class;
784 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
785 pci_bus_read_config(bus, bdf,
786 PCI_SUBSYSTEM_VENDOR_ID,
788 find_id.subvendor = val & 0xffff;
789 find_id.subdevice = val >> 16;
791 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
799 /* Update the platform data */
800 pplat = dev_get_parent_platdata(dev);
801 pplat->devfn = PCI_MASK_BUS(bdf);
802 pplat->vendor = vendor;
803 pplat->device = device;
804 pplat->class = class;
809 printf("Cannot read bus configuration: %d\n", ret);
814 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
817 int pci_addr_cells, addr_cells, size_cells;
818 int cells_per_record;
823 prop = ofnode_get_property(node, "ranges", &len);
825 debug("%s: Cannot decode regions\n", __func__);
829 pci_addr_cells = ofnode_read_simple_addr_cells(node);
830 addr_cells = ofnode_read_simple_addr_cells(parent_node);
831 size_cells = ofnode_read_simple_size_cells(node);
833 /* PCI addresses are always 3-cells */
835 cells_per_record = pci_addr_cells + addr_cells + size_cells;
836 hose->region_count = 0;
837 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
839 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
840 u64 pci_addr, addr, size;
846 if (len < cells_per_record)
848 flags = fdt32_to_cpu(prop[0]);
849 space_code = (flags >> 24) & 3;
850 pci_addr = fdtdec_get_number(prop + 1, 2);
851 prop += pci_addr_cells;
852 addr = fdtdec_get_number(prop, addr_cells);
854 size = fdtdec_get_number(prop, size_cells);
856 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
857 __func__, hose->region_count, pci_addr, addr, size, space_code);
858 if (space_code & 2) {
859 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
861 } else if (space_code & 1) {
862 type = PCI_REGION_IO;
867 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
868 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
869 debug(" - beyond the 32-bit boundary, ignoring\n");
874 for (i = 0; i < hose->region_count; i++) {
875 if (hose->regions[i].flags == type)
879 pos = hose->region_count++;
880 debug(" - type=%d, pos=%d\n", type, pos);
881 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
884 /* Add a region for our local memory */
885 #ifdef CONFIG_NR_DRAM_BANKS
891 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
892 if (bd->bi_dram[i].size) {
893 pci_set_region(hose->regions + hose->region_count++,
894 bd->bi_dram[i].start,
895 bd->bi_dram[i].start,
897 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
901 phys_addr_t base = 0, size;
904 #ifdef CONFIG_SYS_SDRAM_BASE
905 base = CONFIG_SYS_SDRAM_BASE;
907 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
908 size = gd->pci_ram_top - base;
910 pci_set_region(hose->regions + hose->region_count++, base,
911 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
917 static int pci_uclass_pre_probe(struct udevice *bus)
919 struct pci_controller *hose;
921 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
923 hose = bus->uclass_priv;
925 /* For bridges, use the top-level PCI controller */
926 if (!device_is_on_pci_bus(bus)) {
928 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
930 struct pci_controller *parent_hose;
932 parent_hose = dev_get_uclass_priv(bus->parent);
933 hose->ctlr = parent_hose->bus;
936 hose->first_busno = bus->seq;
937 hose->last_busno = bus->seq;
942 static int pci_uclass_post_probe(struct udevice *bus)
946 debug("%s: probing bus %d\n", __func__, bus->seq);
947 ret = pci_bind_bus_devices(bus);
951 #ifdef CONFIG_PCI_PNP
952 ret = pci_auto_config_devices(bus);
957 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
959 * Per Intel FSP specification, we should call FSP notify API to
960 * inform FSP that PCI enumeration has been done so that FSP will
961 * do any necessary initialization as required by the chipset's
962 * BIOS Writer's Guide (BWG).
964 * Unfortunately we have to put this call here as with driver model,
965 * the enumeration is all done on a lazy basis as needed, so until
966 * something is touched on PCI it won't happen.
968 * Note we only call this 1) after U-Boot is relocated, and 2)
969 * root bus has finished probing.
971 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
972 ret = fsp_init_phase_pci();
981 static int pci_uclass_child_post_bind(struct udevice *dev)
983 struct pci_child_platdata *pplat;
984 struct fdt_pci_addr addr;
987 if (!dev_of_valid(dev))
990 pplat = dev_get_parent_platdata(dev);
992 /* Extract vendor id and device id if available */
993 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
995 /* Extract the devfn from fdt_pci_addr */
996 ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
1002 pplat->devfn = addr.phys_hi & 0xff00;
1008 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
1009 uint offset, ulong *valuep,
1010 enum pci_size_t size)
1012 struct pci_controller *hose = bus->uclass_priv;
1014 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1017 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1018 uint offset, ulong value,
1019 enum pci_size_t size)
1021 struct pci_controller *hose = bus->uclass_priv;
1023 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1026 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1028 struct udevice *dev;
1032 * Scan through all the PCI controllers. On x86 there will only be one
1033 * but that is not necessarily true on other hardware.
1036 device_find_first_child(bus, &dev);
1041 ret = uclass_next_device(&bus);
1049 int pci_find_next_device(struct udevice **devp)
1051 struct udevice *child = *devp;
1052 struct udevice *bus = child->parent;
1055 /* First try all the siblings */
1058 device_find_next_child(&child);
1065 /* We ran out of siblings. Try the next bus */
1066 ret = uclass_next_device(&bus);
1070 return bus ? skip_to_next_device(bus, devp) : 0;
1073 int pci_find_first_device(struct udevice **devp)
1075 struct udevice *bus;
1079 ret = uclass_first_device(UCLASS_PCI, &bus);
1083 return skip_to_next_device(bus, devp);
1086 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1090 return (value >> ((offset & 3) * 8)) & 0xff;
1092 return (value >> ((offset & 2) * 8)) & 0xffff;
1098 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1099 enum pci_size_t size)
1102 uint val_mask, shift;
1117 shift = (offset & off_mask) * 8;
1118 ldata = (value & val_mask) << shift;
1119 mask = val_mask << shift;
1120 value = (old & ~mask) | ldata;
1125 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1126 struct pci_region **memp, struct pci_region **prefp)
1128 struct udevice *bus = pci_get_controller(dev);
1129 struct pci_controller *hose = dev_get_uclass_priv(bus);
1135 for (i = 0; i < hose->region_count; i++) {
1136 switch (hose->regions[i].flags) {
1138 if (!*iop || (*iop)->size < hose->regions[i].size)
1139 *iop = hose->regions + i;
1141 case PCI_REGION_MEM:
1142 if (!*memp || (*memp)->size < hose->regions[i].size)
1143 *memp = hose->regions + i;
1145 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1146 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1147 *prefp = hose->regions + i;
1152 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1155 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1160 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1161 dm_pci_read_config32(dev, bar, &addr);
1162 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1163 return addr & PCI_BASE_ADDRESS_IO_MASK;
1165 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1168 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1172 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1173 dm_pci_write_config32(dev, bar, addr);
1176 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1177 pci_addr_t bus_addr, unsigned long flags,
1178 unsigned long skip_mask, phys_addr_t *pa)
1180 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1181 struct pci_region *res;
1184 if (hose->region_count == 0) {
1189 for (i = 0; i < hose->region_count; i++) {
1190 res = &hose->regions[i];
1192 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1195 if (res->flags & skip_mask)
1198 if (bus_addr >= res->bus_start &&
1199 (bus_addr - res->bus_start) < res->size) {
1200 *pa = (bus_addr - res->bus_start + res->phys_start);
1208 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1209 unsigned long flags)
1211 phys_addr_t phys_addr = 0;
1212 struct udevice *ctlr;
1215 /* The root controller has the region information */
1216 ctlr = pci_get_controller(dev);
1219 * if PCI_REGION_MEM is set we do a two pass search with preference
1220 * on matches that don't have PCI_REGION_SYS_MEMORY set
1222 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1223 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1224 flags, PCI_REGION_SYS_MEMORY,
1230 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1233 puts("pci_hose_bus_to_phys: invalid physical address\n");
1238 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1239 unsigned long flags, unsigned long skip_mask,
1242 struct pci_region *res;
1243 struct udevice *ctlr;
1244 pci_addr_t bus_addr;
1246 struct pci_controller *hose;
1248 /* The root controller has the region information */
1249 ctlr = pci_get_controller(dev);
1250 hose = dev_get_uclass_priv(ctlr);
1252 if (hose->region_count == 0) {
1257 for (i = 0; i < hose->region_count; i++) {
1258 res = &hose->regions[i];
1260 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1263 if (res->flags & skip_mask)
1266 bus_addr = phys_addr - res->phys_start + res->bus_start;
1268 if (bus_addr >= res->bus_start &&
1269 (bus_addr - res->bus_start) < res->size) {
1278 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1279 unsigned long flags)
1281 pci_addr_t bus_addr = 0;
1285 * if PCI_REGION_MEM is set we do a two pass search with preference
1286 * on matches that don't have PCI_REGION_SYS_MEMORY set
1288 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1289 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1290 PCI_REGION_SYS_MEMORY, &bus_addr);
1295 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1298 puts("pci_hose_phys_to_bus: invalid physical address\n");
1303 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1305 pci_addr_t pci_bus_addr;
1308 /* read BAR address */
1309 dm_pci_read_config32(dev, bar, &bar_response);
1310 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1313 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1314 * isn't actualy used on any platform because u-boot assumes a static
1315 * linear mapping. In the future, this could read the BAR size
1316 * and pass that as the size if needed.
1318 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1321 int dm_pci_find_capability(struct udevice *dev, int cap)
1325 int ttl = PCI_FIND_CAP_TTL;
1330 dm_pci_read_config16(dev, PCI_STATUS, &status);
1331 if (!(status & PCI_STATUS_CAP_LIST))
1334 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1335 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1336 pos = PCI_CB_CAPABILITY_LIST;
1338 pos = PCI_CAPABILITY_LIST;
1340 dm_pci_read_config8(dev, pos, &pos);
1342 if (pos < PCI_STD_HEADER_SIZEOF)
1345 dm_pci_read_config16(dev, pos, &ent);
1358 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1362 int pos = PCI_CFG_SPACE_SIZE;
1364 /* minimum 8 bytes per capability */
1365 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1367 dm_pci_read_config32(dev, pos, &header);
1369 * If we have no capabilities, this is indicated by cap ID,
1370 * cap version and next pointer all being 0.
1376 if (PCI_EXT_CAP_ID(header) == cap)
1379 pos = PCI_EXT_CAP_NEXT(header);
1380 if (pos < PCI_CFG_SPACE_SIZE)
1383 dm_pci_read_config32(dev, pos, &header);
1389 UCLASS_DRIVER(pci) = {
1392 .flags = DM_UC_FLAG_SEQ_ALIAS,
1393 .post_bind = dm_scan_fdt_dev,
1394 .pre_probe = pci_uclass_pre_probe,
1395 .post_probe = pci_uclass_post_probe,
1396 .child_post_bind = pci_uclass_child_post_bind,
1397 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1398 .per_child_platdata_auto_alloc_size =
1399 sizeof(struct pci_child_platdata),
1402 static const struct dm_pci_ops pci_bridge_ops = {
1403 .read_config = pci_bridge_read_config,
1404 .write_config = pci_bridge_write_config,
1407 static const struct udevice_id pci_bridge_ids[] = {
1408 { .compatible = "pci-bridge" },
1412 U_BOOT_DRIVER(pci_bridge_drv) = {
1413 .name = "pci_bridge_drv",
1415 .of_match = pci_bridge_ids,
1416 .ops = &pci_bridge_ops,
1419 UCLASS_DRIVER(pci_generic) = {
1420 .id = UCLASS_PCI_GENERIC,
1421 .name = "pci_generic",
1424 static const struct udevice_id pci_generic_ids[] = {
1425 { .compatible = "pci-generic" },
1429 U_BOOT_DRIVER(pci_generic_drv) = {
1430 .name = "pci_generic_drv",
1431 .id = UCLASS_PCI_GENERIC,
1432 .of_match = pci_generic_ids,
1437 struct udevice *bus;
1440 * Enumerate all known controller devices. Enumeration has the side-
1441 * effect of probing them, so PCIe devices will be enumerated too.
1443 for (uclass_first_device(UCLASS_PCI, &bus);
1445 uclass_next_device(&bus)) {