1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
14 #include <dm/device-internal.h>
16 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
17 #include <asm/fsp/fsp_support.h>
19 #include "pci_internal.h"
21 DECLARE_GLOBAL_DATA_PTR;
23 int pci_get_bus(int busnum, struct udevice **busp)
27 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
29 /* Since buses may not be numbered yet try a little harder with bus 0 */
31 ret = uclass_first_device_err(UCLASS_PCI, busp);
34 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
40 struct udevice *pci_get_controller(struct udevice *dev)
42 while (device_is_on_pci_bus(dev))
48 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
50 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
51 struct udevice *bus = dev->parent;
54 * This error indicates that @dev is a device on an unprobed PCI bus.
55 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
56 * will produce a bad BDF>
58 * A common cause of this problem is that this function is called in the
59 * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
60 * method is not allowed, since it has not yet been probed. To fix this,
61 * move that access to the probe() method of @dev instead.
63 if (!device_active(bus))
64 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
66 return PCI_ADD_BUS(bus->seq, pplat->devfn);
70 * pci_get_bus_max() - returns the bus number of the last active bus
72 * @return last bus number, or -1 if no active buses
74 static int pci_get_bus_max(void)
80 ret = uclass_get(UCLASS_PCI, &uc);
81 uclass_foreach_dev(bus, uc) {
86 debug("%s: ret=%d\n", __func__, ret);
91 int pci_last_busno(void)
93 return pci_get_bus_max();
96 int pci_get_ff(enum pci_size_t size)
108 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
111 struct fdt_pci_addr addr;
115 dev_for_each_subnode(node, bus) {
116 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
121 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
129 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
130 struct udevice **devp)
134 for (device_find_first_child(bus, &dev);
136 device_find_next_child(&dev)) {
137 struct pci_child_platdata *pplat;
139 pplat = dev_get_parent_platdata(dev);
140 if (pplat && pplat->devfn == find_devfn) {
149 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
154 ret = pci_get_bus(PCI_BUS(bdf), &bus);
157 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
160 static int pci_device_matches_ids(struct udevice *dev,
161 struct pci_device_id *ids)
163 struct pci_child_platdata *pplat;
166 pplat = dev_get_parent_platdata(dev);
169 for (i = 0; ids[i].vendor != 0; i++) {
170 if (pplat->vendor == ids[i].vendor &&
171 pplat->device == ids[i].device)
178 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
179 int *indexp, struct udevice **devp)
183 /* Scan all devices on this bus */
184 for (device_find_first_child(bus, &dev);
186 device_find_next_child(&dev)) {
187 if (pci_device_matches_ids(dev, ids) >= 0) {
188 if ((*indexp)-- <= 0) {
198 int pci_find_device_id(struct pci_device_id *ids, int index,
199 struct udevice **devp)
203 /* Scan all known buses */
204 for (uclass_first_device(UCLASS_PCI, &bus);
206 uclass_next_device(&bus)) {
207 if (!pci_bus_find_devices(bus, ids, &index, devp))
215 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
216 unsigned int device, int *indexp,
217 struct udevice **devp)
219 struct pci_child_platdata *pplat;
222 for (device_find_first_child(bus, &dev);
224 device_find_next_child(&dev)) {
225 pplat = dev_get_parent_platdata(dev);
226 if (pplat->vendor == vendor && pplat->device == device) {
237 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
238 struct udevice **devp)
242 /* Scan all known buses */
243 for (uclass_first_device(UCLASS_PCI, &bus);
245 uclass_next_device(&bus)) {
246 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
247 return device_probe(*devp);
254 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
258 /* Scan all known buses */
259 for (pci_find_first_device(&dev);
261 pci_find_next_device(&dev)) {
262 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
264 if (pplat->class == find_class && !index--) {
266 return device_probe(*devp);
274 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
275 unsigned long value, enum pci_size_t size)
277 struct dm_pci_ops *ops;
279 ops = pci_get_ops(bus);
280 if (!ops->write_config)
282 return ops->write_config(bus, bdf, offset, value, size);
285 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
291 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
297 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
300 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
301 enum pci_size_t size)
306 ret = pci_get_bus(PCI_BUS(bdf), &bus);
310 return pci_bus_write_config(bus, bdf, offset, value, size);
313 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
314 enum pci_size_t size)
318 for (bus = dev; device_is_on_pci_bus(bus);)
320 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
324 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
326 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
329 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
331 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
334 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
336 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
339 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
341 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
344 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
346 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
349 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
351 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
354 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
355 unsigned long *valuep, enum pci_size_t size)
357 struct dm_pci_ops *ops;
359 ops = pci_get_ops(bus);
360 if (!ops->read_config)
362 return ops->read_config(bus, bdf, offset, valuep, size);
365 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
366 enum pci_size_t size)
371 ret = pci_get_bus(PCI_BUS(bdf), &bus);
375 return pci_bus_read_config(bus, bdf, offset, valuep, size);
378 int dm_pci_read_config(const struct udevice *dev, int offset,
379 unsigned long *valuep, enum pci_size_t size)
381 const struct udevice *bus;
383 for (bus = dev; device_is_on_pci_bus(bus);)
385 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
389 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
394 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
402 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
407 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
415 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
420 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
428 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
433 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
441 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
446 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
454 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
459 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
467 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
472 ret = dm_pci_read_config8(dev, offset, &val);
478 return dm_pci_write_config8(dev, offset, val);
481 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
486 ret = dm_pci_read_config16(dev, offset, &val);
492 return dm_pci_write_config16(dev, offset, val);
495 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
500 ret = dm_pci_read_config32(dev, offset, &val);
506 return dm_pci_write_config32(dev, offset, val);
509 static void set_vga_bridge_bits(struct udevice *dev)
511 struct udevice *parent = dev->parent;
514 while (parent->seq != 0) {
515 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
516 bc |= PCI_BRIDGE_CTL_VGA;
517 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
518 parent = parent->parent;
522 int pci_auto_config_devices(struct udevice *bus)
524 struct pci_controller *hose = bus->uclass_priv;
525 struct pci_child_platdata *pplat;
526 unsigned int sub_bus;
531 debug("%s: start\n", __func__);
532 pciauto_config_init(hose);
533 for (ret = device_find_first_child(bus, &dev);
535 ret = device_find_next_child(&dev)) {
536 unsigned int max_bus;
539 debug("%s: device %s\n", __func__, dev->name);
540 if (dev_read_bool(dev, "pci,no-autoconfig"))
542 ret = dm_pciauto_config_device(dev);
546 sub_bus = max(sub_bus, max_bus);
548 pplat = dev_get_parent_platdata(dev);
549 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
550 set_vga_bridge_bits(dev);
552 debug("%s: done\n", __func__);
557 int pci_generic_mmap_write_config(
558 const struct udevice *bus,
559 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
564 enum pci_size_t size)
568 if (addr_f(bus, bdf, offset, &address) < 0)
573 writeb(value, address);
576 writew(value, address);
579 writel(value, address);
586 int pci_generic_mmap_read_config(
587 const struct udevice *bus,
588 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
593 enum pci_size_t size)
597 if (addr_f(bus, bdf, offset, &address) < 0) {
598 *valuep = pci_get_ff(size);
604 *valuep = readb(address);
607 *valuep = readw(address);
610 *valuep = readl(address);
617 int dm_pci_hose_probe_bus(struct udevice *bus)
622 debug("%s\n", __func__);
624 sub_bus = pci_get_bus_max() + 1;
625 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
626 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
628 ret = device_probe(bus);
630 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
634 if (sub_bus != bus->seq) {
635 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
636 __func__, bus->name, bus->seq, sub_bus);
639 sub_bus = pci_get_bus_max();
640 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
646 * pci_match_one_device - Tell if a PCI device structure has a matching
647 * PCI device id structure
648 * @id: single PCI device id structure to match
649 * @find: the PCI device id structure to match against
651 * Returns true if the finding pci_device_id structure matched or false if
654 static bool pci_match_one_id(const struct pci_device_id *id,
655 const struct pci_device_id *find)
657 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
658 (id->device == PCI_ANY_ID || id->device == find->device) &&
659 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
660 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
661 !((id->class ^ find->class) & id->class_mask))
668 * pci_find_and_bind_driver() - Find and bind the right PCI driver
670 * This only looks at certain fields in the descriptor.
672 * @parent: Parent bus
673 * @find_id: Specification of the driver to find
674 * @bdf: Bus/device/function addreess - see PCI_BDF()
675 * @devp: Returns a pointer to the device created
676 * @return 0 if OK, -EPERM if the device is not needed before relocation and
677 * therefore was not created, other -ve value on error
679 static int pci_find_and_bind_driver(struct udevice *parent,
680 struct pci_device_id *find_id,
681 pci_dev_t bdf, struct udevice **devp)
683 struct pci_driver_entry *start, *entry;
684 ofnode node = ofnode_null();
693 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
694 find_id->vendor, find_id->device);
696 /* Determine optional OF node */
697 pci_dev_find_ofnode(parent, bdf, &node);
699 if (ofnode_valid(node) && !ofnode_is_available(node)) {
700 debug("%s: Ignoring disabled device\n", __func__);
704 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
705 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
706 for (entry = start; entry != start + n_ents; entry++) {
707 const struct pci_device_id *id;
709 const struct driver *drv;
711 for (id = entry->match;
712 id->vendor || id->subvendor || id->class_mask;
714 if (!pci_match_one_id(id, find_id))
720 * In the pre-relocation phase, we only bind devices
721 * whose driver has the DM_FLAG_PRE_RELOC set, to save
722 * precious memory space as on some platforms as that
723 * space is pretty limited (ie: using Cache As RAM).
725 if (!(gd->flags & GD_FLG_RELOC) &&
726 !(drv->flags & DM_FLAG_PRE_RELOC))
730 * We could pass the descriptor to the driver as
731 * platdata (instead of NULL) and allow its bind()
732 * method to return -ENOENT if it doesn't support this
733 * device. That way we could continue the search to
734 * find another driver. For now this doesn't seem
735 * necesssary, so just bind the first match.
737 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
741 debug("%s: Match found: %s\n", __func__, drv->name);
742 dev->driver_data = id->driver_data;
748 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
750 * In the pre-relocation phase, we only bind bridge devices to save
751 * precious memory space as on some platforms as that space is pretty
752 * limited (ie: using Cache As RAM).
754 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
757 /* Bind a generic driver so that the device can be used */
758 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
763 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
765 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
767 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
771 debug("%s: No match found: bound generic driver instead\n", __func__);
776 debug("%s: No match found: error %d\n", __func__, ret);
780 int pci_bind_bus_devices(struct udevice *bus)
782 ulong vendor, device;
789 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
790 PCI_MAX_PCI_FUNCTIONS - 1);
791 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
792 bdf += PCI_BDF(0, 0, 1)) {
793 struct pci_child_platdata *pplat;
799 if (PCI_FUNC(bdf) && !found_multi)
802 /* Check only the first access, we don't expect problems */
803 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
808 if (vendor == 0xffff || vendor == 0x0000)
811 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
812 &header_type, PCI_SIZE_8);
815 found_multi = header_type & 0x80;
817 debug("%s: bus %d/%s: found device %x, function %d", __func__,
818 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
819 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
821 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
825 /* Find this device in the device tree */
826 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
827 debug(": find ret=%d\n", ret);
829 /* If nothing in the device tree, bind a device */
830 if (ret == -ENODEV) {
831 struct pci_device_id find_id;
834 memset(&find_id, '\0', sizeof(find_id));
835 find_id.vendor = vendor;
836 find_id.device = device;
837 find_id.class = class;
838 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
839 pci_bus_read_config(bus, bdf,
840 PCI_SUBSYSTEM_VENDOR_ID,
842 find_id.subvendor = val & 0xffff;
843 find_id.subdevice = val >> 16;
845 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
853 /* Update the platform data */
854 pplat = dev_get_parent_platdata(dev);
855 pplat->devfn = PCI_MASK_BUS(bdf);
856 pplat->vendor = vendor;
857 pplat->device = device;
858 pplat->class = class;
863 printf("Cannot read bus configuration: %d\n", ret);
868 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
871 int pci_addr_cells, addr_cells, size_cells;
872 int cells_per_record;
877 prop = ofnode_get_property(node, "ranges", &len);
879 debug("%s: Cannot decode regions\n", __func__);
883 pci_addr_cells = ofnode_read_simple_addr_cells(node);
884 addr_cells = ofnode_read_simple_addr_cells(parent_node);
885 size_cells = ofnode_read_simple_size_cells(node);
887 /* PCI addresses are always 3-cells */
889 cells_per_record = pci_addr_cells + addr_cells + size_cells;
890 hose->region_count = 0;
891 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
893 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
894 u64 pci_addr, addr, size;
900 if (len < cells_per_record)
902 flags = fdt32_to_cpu(prop[0]);
903 space_code = (flags >> 24) & 3;
904 pci_addr = fdtdec_get_number(prop + 1, 2);
905 prop += pci_addr_cells;
906 addr = fdtdec_get_number(prop, addr_cells);
908 size = fdtdec_get_number(prop, size_cells);
910 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
911 __func__, hose->region_count, pci_addr, addr, size, space_code);
912 if (space_code & 2) {
913 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
915 } else if (space_code & 1) {
916 type = PCI_REGION_IO;
921 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
922 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
923 debug(" - beyond the 32-bit boundary, ignoring\n");
928 for (i = 0; i < hose->region_count; i++) {
929 if (hose->regions[i].flags == type)
933 pos = hose->region_count++;
934 debug(" - type=%d, pos=%d\n", type, pos);
935 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
938 /* Add a region for our local memory */
939 #ifdef CONFIG_NR_DRAM_BANKS
945 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
946 if (hose->region_count == MAX_PCI_REGIONS) {
947 pr_err("maximum number of regions parsed, aborting\n");
951 if (bd->bi_dram[i].size) {
952 pci_set_region(hose->regions + hose->region_count++,
953 bd->bi_dram[i].start,
954 bd->bi_dram[i].start,
956 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
960 phys_addr_t base = 0, size;
963 #ifdef CONFIG_SYS_SDRAM_BASE
964 base = CONFIG_SYS_SDRAM_BASE;
966 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
967 size = gd->pci_ram_top - base;
969 pci_set_region(hose->regions + hose->region_count++, base,
970 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
976 static int pci_uclass_pre_probe(struct udevice *bus)
978 struct pci_controller *hose;
980 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
982 hose = bus->uclass_priv;
984 /* For bridges, use the top-level PCI controller */
985 if (!device_is_on_pci_bus(bus)) {
987 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
989 struct pci_controller *parent_hose;
991 parent_hose = dev_get_uclass_priv(bus->parent);
992 hose->ctlr = parent_hose->bus;
995 hose->first_busno = bus->seq;
996 hose->last_busno = bus->seq;
997 hose->skip_auto_config_until_reloc =
998 dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
1003 static int pci_uclass_post_probe(struct udevice *bus)
1005 struct pci_controller *hose = dev_get_uclass_priv(bus);
1008 debug("%s: probing bus %d\n", __func__, bus->seq);
1009 ret = pci_bind_bus_devices(bus);
1013 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1014 (!hose->skip_auto_config_until_reloc ||
1015 (gd->flags & GD_FLG_RELOC))) {
1016 ret = pci_auto_config_devices(bus);
1018 return log_msg_ret("pci auto-config", ret);
1021 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1023 * Per Intel FSP specification, we should call FSP notify API to
1024 * inform FSP that PCI enumeration has been done so that FSP will
1025 * do any necessary initialization as required by the chipset's
1026 * BIOS Writer's Guide (BWG).
1028 * Unfortunately we have to put this call here as with driver model,
1029 * the enumeration is all done on a lazy basis as needed, so until
1030 * something is touched on PCI it won't happen.
1032 * Note we only call this 1) after U-Boot is relocated, and 2)
1033 * root bus has finished probing.
1035 if ((gd->flags & GD_FLG_RELOC) && bus->seq == 0 && ll_boot_init()) {
1036 ret = fsp_init_phase_pci();
1045 static int pci_uclass_child_post_bind(struct udevice *dev)
1047 struct pci_child_platdata *pplat;
1049 if (!dev_of_valid(dev))
1052 pplat = dev_get_parent_platdata(dev);
1054 /* Extract vendor id and device id if available */
1055 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1057 /* Extract the devfn from fdt_pci_addr */
1058 pplat->devfn = pci_get_devfn(dev);
1063 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1064 uint offset, ulong *valuep,
1065 enum pci_size_t size)
1067 struct pci_controller *hose = bus->uclass_priv;
1069 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1072 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1073 uint offset, ulong value,
1074 enum pci_size_t size)
1076 struct pci_controller *hose = bus->uclass_priv;
1078 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1081 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1083 struct udevice *dev;
1087 * Scan through all the PCI controllers. On x86 there will only be one
1088 * but that is not necessarily true on other hardware.
1091 device_find_first_child(bus, &dev);
1096 ret = uclass_next_device(&bus);
1104 int pci_find_next_device(struct udevice **devp)
1106 struct udevice *child = *devp;
1107 struct udevice *bus = child->parent;
1110 /* First try all the siblings */
1113 device_find_next_child(&child);
1120 /* We ran out of siblings. Try the next bus */
1121 ret = uclass_next_device(&bus);
1125 return bus ? skip_to_next_device(bus, devp) : 0;
1128 int pci_find_first_device(struct udevice **devp)
1130 struct udevice *bus;
1134 ret = uclass_first_device(UCLASS_PCI, &bus);
1138 return skip_to_next_device(bus, devp);
1141 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1145 return (value >> ((offset & 3) * 8)) & 0xff;
1147 return (value >> ((offset & 2) * 8)) & 0xffff;
1153 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1154 enum pci_size_t size)
1157 uint val_mask, shift;
1172 shift = (offset & off_mask) * 8;
1173 ldata = (value & val_mask) << shift;
1174 mask = val_mask << shift;
1175 value = (old & ~mask) | ldata;
1180 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1181 struct pci_region **memp, struct pci_region **prefp)
1183 struct udevice *bus = pci_get_controller(dev);
1184 struct pci_controller *hose = dev_get_uclass_priv(bus);
1190 for (i = 0; i < hose->region_count; i++) {
1191 switch (hose->regions[i].flags) {
1193 if (!*iop || (*iop)->size < hose->regions[i].size)
1194 *iop = hose->regions + i;
1196 case PCI_REGION_MEM:
1197 if (!*memp || (*memp)->size < hose->regions[i].size)
1198 *memp = hose->regions + i;
1200 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1201 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1202 *prefp = hose->regions + i;
1207 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1210 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1215 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1216 dm_pci_read_config32(dev, bar, &addr);
1219 * If we get an invalid address, return this so that comparisons with
1220 * FDT_ADDR_T_NONE work correctly
1222 if (addr == 0xffffffff)
1224 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1225 return addr & PCI_BASE_ADDRESS_IO_MASK;
1227 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1230 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1234 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1235 dm_pci_write_config32(dev, bar, addr);
1238 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1239 pci_addr_t bus_addr, unsigned long flags,
1240 unsigned long skip_mask, phys_addr_t *pa)
1242 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1243 struct pci_region *res;
1246 if (hose->region_count == 0) {
1251 for (i = 0; i < hose->region_count; i++) {
1252 res = &hose->regions[i];
1254 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1257 if (res->flags & skip_mask)
1260 if (bus_addr >= res->bus_start &&
1261 (bus_addr - res->bus_start) < res->size) {
1262 *pa = (bus_addr - res->bus_start + res->phys_start);
1270 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1271 unsigned long flags)
1273 phys_addr_t phys_addr = 0;
1274 struct udevice *ctlr;
1277 /* The root controller has the region information */
1278 ctlr = pci_get_controller(dev);
1281 * if PCI_REGION_MEM is set we do a two pass search with preference
1282 * on matches that don't have PCI_REGION_SYS_MEMORY set
1284 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1285 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1286 flags, PCI_REGION_SYS_MEMORY,
1292 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1295 puts("pci_hose_bus_to_phys: invalid physical address\n");
1300 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1301 unsigned long flags, unsigned long skip_mask,
1304 struct pci_region *res;
1305 struct udevice *ctlr;
1306 pci_addr_t bus_addr;
1308 struct pci_controller *hose;
1310 /* The root controller has the region information */
1311 ctlr = pci_get_controller(dev);
1312 hose = dev_get_uclass_priv(ctlr);
1314 if (hose->region_count == 0) {
1319 for (i = 0; i < hose->region_count; i++) {
1320 res = &hose->regions[i];
1322 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1325 if (res->flags & skip_mask)
1328 bus_addr = phys_addr - res->phys_start + res->bus_start;
1330 if (bus_addr >= res->bus_start &&
1331 (bus_addr - res->bus_start) < res->size) {
1340 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1341 unsigned long flags)
1343 pci_addr_t bus_addr = 0;
1347 * if PCI_REGION_MEM is set we do a two pass search with preference
1348 * on matches that don't have PCI_REGION_SYS_MEMORY set
1350 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1351 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1352 PCI_REGION_SYS_MEMORY, &bus_addr);
1357 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1360 puts("pci_hose_phys_to_bus: invalid physical address\n");
1365 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1368 int ea_cnt, i, entry_size;
1369 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1373 /* EA capability structure header */
1374 dm_pci_read_config32(dev, ea_off, &ea_entry);
1375 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1376 ea_off += PCI_EA_FIRST_ENT;
1378 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1380 dm_pci_read_config32(dev, ea_off, &ea_entry);
1381 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1383 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1386 /* Base address, 1st DW */
1387 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1388 addr = ea_entry & PCI_EA_FIELD_MASK;
1389 if (ea_entry & PCI_EA_IS_64) {
1390 /* Base address, 2nd DW, skip over 4B MaxOffset */
1391 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1392 addr |= ((u64)ea_entry) << 32;
1395 /* size ignored for now */
1396 return map_physmem(addr, flags, 0);
1402 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1404 pci_addr_t pci_bus_addr;
1409 * if the function supports Enhanced Allocation use that instead of
1412 ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
1414 return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
1416 /* read BAR address */
1417 dm_pci_read_config32(dev, bar, &bar_response);
1418 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1421 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1422 * isn't actualy used on any platform because u-boot assumes a static
1423 * linear mapping. In the future, this could read the BAR size
1424 * and pass that as the size if needed.
1426 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1429 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1431 int ttl = PCI_FIND_CAP_TTL;
1435 dm_pci_read_config8(dev, pos, &pos);
1438 if (pos < PCI_STD_HEADER_SIZEOF)
1441 dm_pci_read_config16(dev, pos, &ent);
1454 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1456 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1460 int dm_pci_find_capability(struct udevice *dev, int cap)
1466 dm_pci_read_config16(dev, PCI_STATUS, &status);
1467 if (!(status & PCI_STATUS_CAP_LIST))
1470 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1471 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1472 pos = PCI_CB_CAPABILITY_LIST;
1474 pos = PCI_CAPABILITY_LIST;
1476 return _dm_pci_find_next_capability(dev, pos, cap);
1479 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1483 int pos = PCI_CFG_SPACE_SIZE;
1485 /* minimum 8 bytes per capability */
1486 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1491 dm_pci_read_config32(dev, pos, &header);
1493 * If we have no capabilities, this is indicated by cap ID,
1494 * cap version and next pointer all being 0.
1500 if (PCI_EXT_CAP_ID(header) == cap)
1503 pos = PCI_EXT_CAP_NEXT(header);
1504 if (pos < PCI_CFG_SPACE_SIZE)
1507 dm_pci_read_config32(dev, pos, &header);
1513 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1515 return dm_pci_find_next_ext_capability(dev, 0, cap);
1518 int dm_pci_flr(struct udevice *dev)
1523 /* look for PCI Express Capability */
1524 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1528 /* check FLR capability */
1529 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1530 if (!(cap & PCI_EXP_DEVCAP_FLR))
1533 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1534 PCI_EXP_DEVCTL_BCR_FLR);
1536 /* wait 100ms, per PCI spec */
1542 UCLASS_DRIVER(pci) = {
1545 .flags = DM_UC_FLAG_SEQ_ALIAS,
1546 .post_bind = dm_scan_fdt_dev,
1547 .pre_probe = pci_uclass_pre_probe,
1548 .post_probe = pci_uclass_post_probe,
1549 .child_post_bind = pci_uclass_child_post_bind,
1550 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1551 .per_child_platdata_auto_alloc_size =
1552 sizeof(struct pci_child_platdata),
1555 static const struct dm_pci_ops pci_bridge_ops = {
1556 .read_config = pci_bridge_read_config,
1557 .write_config = pci_bridge_write_config,
1560 static const struct udevice_id pci_bridge_ids[] = {
1561 { .compatible = "pci-bridge" },
1565 U_BOOT_DRIVER(pci_bridge_drv) = {
1566 .name = "pci_bridge_drv",
1568 .of_match = pci_bridge_ids,
1569 .ops = &pci_bridge_ops,
1572 UCLASS_DRIVER(pci_generic) = {
1573 .id = UCLASS_PCI_GENERIC,
1574 .name = "pci_generic",
1577 static const struct udevice_id pci_generic_ids[] = {
1578 { .compatible = "pci-generic" },
1582 U_BOOT_DRIVER(pci_generic_drv) = {
1583 .name = "pci_generic_drv",
1584 .id = UCLASS_PCI_GENERIC,
1585 .of_match = pci_generic_ids,
1590 struct udevice *bus;
1593 * Enumerate all known controller devices. Enumeration has the side-
1594 * effect of probing them, so PCIe devices will be enumerated too.
1596 for (uclass_first_device_check(UCLASS_PCI, &bus);
1598 uclass_next_device_check(&bus)) {