1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
13 #include <dm/device-internal.h>
15 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
16 #include <asm/fsp/fsp_support.h>
18 #include "pci_internal.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 int pci_get_bus(int busnum, struct udevice **busp)
26 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
28 /* Since buses may not be numbered yet try a little harder with bus 0 */
30 ret = uclass_first_device_err(UCLASS_PCI, busp);
33 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
39 struct udevice *pci_get_controller(struct udevice *dev)
41 while (device_is_on_pci_bus(dev))
47 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
49 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
50 struct udevice *bus = dev->parent;
52 return PCI_ADD_BUS(bus->seq, pplat->devfn);
56 * pci_get_bus_max() - returns the bus number of the last active bus
58 * @return last bus number, or -1 if no active buses
60 static int pci_get_bus_max(void)
66 ret = uclass_get(UCLASS_PCI, &uc);
67 uclass_foreach_dev(bus, uc) {
72 debug("%s: ret=%d\n", __func__, ret);
77 int pci_last_busno(void)
79 return pci_get_bus_max();
82 int pci_get_ff(enum pci_size_t size)
94 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
95 struct udevice **devp)
99 for (device_find_first_child(bus, &dev);
101 device_find_next_child(&dev)) {
102 struct pci_child_platdata *pplat;
104 pplat = dev_get_parent_platdata(dev);
105 if (pplat && pplat->devfn == find_devfn) {
114 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
119 ret = pci_get_bus(PCI_BUS(bdf), &bus);
122 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
125 static int pci_device_matches_ids(struct udevice *dev,
126 struct pci_device_id *ids)
128 struct pci_child_platdata *pplat;
131 pplat = dev_get_parent_platdata(dev);
134 for (i = 0; ids[i].vendor != 0; i++) {
135 if (pplat->vendor == ids[i].vendor &&
136 pplat->device == ids[i].device)
143 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
144 int *indexp, struct udevice **devp)
148 /* Scan all devices on this bus */
149 for (device_find_first_child(bus, &dev);
151 device_find_next_child(&dev)) {
152 if (pci_device_matches_ids(dev, ids) >= 0) {
153 if ((*indexp)-- <= 0) {
163 int pci_find_device_id(struct pci_device_id *ids, int index,
164 struct udevice **devp)
168 /* Scan all known buses */
169 for (uclass_first_device(UCLASS_PCI, &bus);
171 uclass_next_device(&bus)) {
172 if (!pci_bus_find_devices(bus, ids, &index, devp))
180 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
181 unsigned int device, int *indexp,
182 struct udevice **devp)
184 struct pci_child_platdata *pplat;
187 for (device_find_first_child(bus, &dev);
189 device_find_next_child(&dev)) {
190 pplat = dev_get_parent_platdata(dev);
191 if (pplat->vendor == vendor && pplat->device == device) {
202 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
203 struct udevice **devp)
207 /* Scan all known buses */
208 for (uclass_first_device(UCLASS_PCI, &bus);
210 uclass_next_device(&bus)) {
211 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
212 return device_probe(*devp);
219 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
223 /* Scan all known buses */
224 for (pci_find_first_device(&dev);
226 pci_find_next_device(&dev)) {
227 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
229 if (pplat->class == find_class && !index--) {
231 return device_probe(*devp);
239 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
240 unsigned long value, enum pci_size_t size)
242 struct dm_pci_ops *ops;
244 ops = pci_get_ops(bus);
245 if (!ops->write_config)
247 return ops->write_config(bus, bdf, offset, value, size);
250 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
256 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
262 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
265 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
266 enum pci_size_t size)
271 ret = pci_get_bus(PCI_BUS(bdf), &bus);
275 return pci_bus_write_config(bus, bdf, offset, value, size);
278 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
279 enum pci_size_t size)
283 for (bus = dev; device_is_on_pci_bus(bus);)
285 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
289 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
291 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
294 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
296 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
299 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
301 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
304 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
306 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
309 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
311 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
314 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
316 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
319 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
320 unsigned long *valuep, enum pci_size_t size)
322 struct dm_pci_ops *ops;
324 ops = pci_get_ops(bus);
325 if (!ops->read_config)
327 return ops->read_config(bus, bdf, offset, valuep, size);
330 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
331 enum pci_size_t size)
336 ret = pci_get_bus(PCI_BUS(bdf), &bus);
340 return pci_bus_read_config(bus, bdf, offset, valuep, size);
343 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
344 enum pci_size_t size)
348 for (bus = dev; device_is_on_pci_bus(bus);)
350 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
354 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
359 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
367 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
372 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
380 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
385 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
393 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
398 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
406 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
411 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
419 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
424 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
432 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
437 ret = dm_pci_read_config8(dev, offset, &val);
443 return dm_pci_write_config8(dev, offset, val);
446 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
451 ret = dm_pci_read_config16(dev, offset, &val);
457 return dm_pci_write_config16(dev, offset, val);
460 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
465 ret = dm_pci_read_config32(dev, offset, &val);
471 return dm_pci_write_config32(dev, offset, val);
474 static void set_vga_bridge_bits(struct udevice *dev)
476 struct udevice *parent = dev->parent;
479 while (parent->seq != 0) {
480 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
481 bc |= PCI_BRIDGE_CTL_VGA;
482 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
483 parent = parent->parent;
487 int pci_auto_config_devices(struct udevice *bus)
489 struct pci_controller *hose = bus->uclass_priv;
490 struct pci_child_platdata *pplat;
491 unsigned int sub_bus;
496 debug("%s: start\n", __func__);
497 pciauto_config_init(hose);
498 for (ret = device_find_first_child(bus, &dev);
500 ret = device_find_next_child(&dev)) {
501 unsigned int max_bus;
504 debug("%s: device %s\n", __func__, dev->name);
505 ret = dm_pciauto_config_device(dev);
509 sub_bus = max(sub_bus, max_bus);
511 pplat = dev_get_parent_platdata(dev);
512 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
513 set_vga_bridge_bits(dev);
515 debug("%s: done\n", __func__);
520 int pci_generic_mmap_write_config(
522 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
526 enum pci_size_t size)
530 if (addr_f(bus, bdf, offset, &address) < 0)
535 writeb(value, address);
538 writew(value, address);
541 writel(value, address);
548 int pci_generic_mmap_read_config(
550 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
554 enum pci_size_t size)
558 if (addr_f(bus, bdf, offset, &address) < 0) {
559 *valuep = pci_get_ff(size);
565 *valuep = readb(address);
568 *valuep = readw(address);
571 *valuep = readl(address);
578 int dm_pci_hose_probe_bus(struct udevice *bus)
583 debug("%s\n", __func__);
585 sub_bus = pci_get_bus_max() + 1;
586 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
587 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
589 ret = device_probe(bus);
591 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
595 if (sub_bus != bus->seq) {
596 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
597 __func__, bus->name, bus->seq, sub_bus);
600 sub_bus = pci_get_bus_max();
601 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
607 * pci_match_one_device - Tell if a PCI device structure has a matching
608 * PCI device id structure
609 * @id: single PCI device id structure to match
610 * @find: the PCI device id structure to match against
612 * Returns true if the finding pci_device_id structure matched or false if
615 static bool pci_match_one_id(const struct pci_device_id *id,
616 const struct pci_device_id *find)
618 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
619 (id->device == PCI_ANY_ID || id->device == find->device) &&
620 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
621 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
622 !((id->class ^ find->class) & id->class_mask))
629 * pci_find_and_bind_driver() - Find and bind the right PCI driver
631 * This only looks at certain fields in the descriptor.
633 * @parent: Parent bus
634 * @find_id: Specification of the driver to find
635 * @bdf: Bus/device/function addreess - see PCI_BDF()
636 * @devp: Returns a pointer to the device created
637 * @return 0 if OK, -EPERM if the device is not needed before relocation and
638 * therefore was not created, other -ve value on error
640 static int pci_find_and_bind_driver(struct udevice *parent,
641 struct pci_device_id *find_id,
642 pci_dev_t bdf, struct udevice **devp)
644 struct pci_driver_entry *start, *entry;
653 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
654 find_id->vendor, find_id->device);
655 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
656 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
657 for (entry = start; entry != start + n_ents; entry++) {
658 const struct pci_device_id *id;
660 const struct driver *drv;
662 for (id = entry->match;
663 id->vendor || id->subvendor || id->class_mask;
665 if (!pci_match_one_id(id, find_id))
671 * In the pre-relocation phase, we only bind devices
672 * whose driver has the DM_FLAG_PRE_RELOC set, to save
673 * precious memory space as on some platforms as that
674 * space is pretty limited (ie: using Cache As RAM).
676 if (!(gd->flags & GD_FLG_RELOC) &&
677 !(drv->flags & DM_FLAG_PRE_RELOC))
681 * We could pass the descriptor to the driver as
682 * platdata (instead of NULL) and allow its bind()
683 * method to return -ENOENT if it doesn't support this
684 * device. That way we could continue the search to
685 * find another driver. For now this doesn't seem
686 * necesssary, so just bind the first match.
688 ret = device_bind(parent, drv, drv->name, NULL, -1,
692 debug("%s: Match found: %s\n", __func__, drv->name);
693 dev->driver_data = id->driver_data;
699 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
701 * In the pre-relocation phase, we only bind bridge devices to save
702 * precious memory space as on some platforms as that space is pretty
703 * limited (ie: using Cache As RAM).
705 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
708 /* Bind a generic driver so that the device can be used */
709 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
714 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
716 ret = device_bind_driver(parent, drv, str, devp);
718 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
722 debug("%s: No match found: bound generic driver instead\n", __func__);
727 debug("%s: No match found: error %d\n", __func__, ret);
731 int pci_bind_bus_devices(struct udevice *bus)
733 ulong vendor, device;
740 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
741 PCI_MAX_PCI_FUNCTIONS - 1);
742 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
743 bdf += PCI_BDF(0, 0, 1)) {
744 struct pci_child_platdata *pplat;
750 if (PCI_FUNC(bdf) && !found_multi)
752 /* Check only the first access, we don't expect problems */
753 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
754 &header_type, PCI_SIZE_8);
757 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
759 if (vendor == 0xffff || vendor == 0x0000)
763 found_multi = header_type & 0x80;
765 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
766 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
767 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
769 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
773 /* Find this device in the device tree */
774 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
776 /* If nothing in the device tree, bind a device */
777 if (ret == -ENODEV) {
778 struct pci_device_id find_id;
781 memset(&find_id, '\0', sizeof(find_id));
782 find_id.vendor = vendor;
783 find_id.device = device;
784 find_id.class = class;
785 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
786 pci_bus_read_config(bus, bdf,
787 PCI_SUBSYSTEM_VENDOR_ID,
789 find_id.subvendor = val & 0xffff;
790 find_id.subdevice = val >> 16;
792 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
800 /* Update the platform data */
801 pplat = dev_get_parent_platdata(dev);
802 pplat->devfn = PCI_MASK_BUS(bdf);
803 pplat->vendor = vendor;
804 pplat->device = device;
805 pplat->class = class;
810 printf("Cannot read bus configuration: %d\n", ret);
815 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
818 int pci_addr_cells, addr_cells, size_cells;
819 int cells_per_record;
824 prop = ofnode_get_property(node, "ranges", &len);
826 debug("%s: Cannot decode regions\n", __func__);
830 pci_addr_cells = ofnode_read_simple_addr_cells(node);
831 addr_cells = ofnode_read_simple_addr_cells(parent_node);
832 size_cells = ofnode_read_simple_size_cells(node);
834 /* PCI addresses are always 3-cells */
836 cells_per_record = pci_addr_cells + addr_cells + size_cells;
837 hose->region_count = 0;
838 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
840 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
841 u64 pci_addr, addr, size;
847 if (len < cells_per_record)
849 flags = fdt32_to_cpu(prop[0]);
850 space_code = (flags >> 24) & 3;
851 pci_addr = fdtdec_get_number(prop + 1, 2);
852 prop += pci_addr_cells;
853 addr = fdtdec_get_number(prop, addr_cells);
855 size = fdtdec_get_number(prop, size_cells);
857 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
858 ", size=%" PRIx64 ", space_code=%d\n", __func__,
859 hose->region_count, pci_addr, addr, size, space_code);
860 if (space_code & 2) {
861 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
863 } else if (space_code & 1) {
864 type = PCI_REGION_IO;
869 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
870 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
871 debug(" - beyond the 32-bit boundary, ignoring\n");
876 for (i = 0; i < hose->region_count; i++) {
877 if (hose->regions[i].flags == type)
881 pos = hose->region_count++;
882 debug(" - type=%d, pos=%d\n", type, pos);
883 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
886 /* Add a region for our local memory */
887 #ifdef CONFIG_NR_DRAM_BANKS
893 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
894 if (bd->bi_dram[i].size) {
895 pci_set_region(hose->regions + hose->region_count++,
896 bd->bi_dram[i].start,
897 bd->bi_dram[i].start,
899 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
903 phys_addr_t base = 0, size;
906 #ifdef CONFIG_SYS_SDRAM_BASE
907 base = CONFIG_SYS_SDRAM_BASE;
909 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
910 size = gd->pci_ram_top - base;
912 pci_set_region(hose->regions + hose->region_count++, base,
913 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
919 static int pci_uclass_pre_probe(struct udevice *bus)
921 struct pci_controller *hose;
923 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
925 hose = bus->uclass_priv;
927 /* For bridges, use the top-level PCI controller */
928 if (!device_is_on_pci_bus(bus)) {
930 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
932 struct pci_controller *parent_hose;
934 parent_hose = dev_get_uclass_priv(bus->parent);
935 hose->ctlr = parent_hose->bus;
938 hose->first_busno = bus->seq;
939 hose->last_busno = bus->seq;
944 static int pci_uclass_post_probe(struct udevice *bus)
948 debug("%s: probing bus %d\n", __func__, bus->seq);
949 ret = pci_bind_bus_devices(bus);
953 #ifdef CONFIG_PCI_PNP
954 ret = pci_auto_config_devices(bus);
959 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
961 * Per Intel FSP specification, we should call FSP notify API to
962 * inform FSP that PCI enumeration has been done so that FSP will
963 * do any necessary initialization as required by the chipset's
964 * BIOS Writer's Guide (BWG).
966 * Unfortunately we have to put this call here as with driver model,
967 * the enumeration is all done on a lazy basis as needed, so until
968 * something is touched on PCI it won't happen.
970 * Note we only call this 1) after U-Boot is relocated, and 2)
971 * root bus has finished probing.
973 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
974 ret = fsp_init_phase_pci();
983 static int pci_uclass_child_post_bind(struct udevice *dev)
985 struct pci_child_platdata *pplat;
986 struct fdt_pci_addr addr;
989 if (!dev_of_valid(dev))
992 pplat = dev_get_parent_platdata(dev);
994 /* Extract vendor id and device id if available */
995 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
997 /* Extract the devfn from fdt_pci_addr */
998 ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
1004 pplat->devfn = addr.phys_hi & 0xff00;
1010 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
1011 uint offset, ulong *valuep,
1012 enum pci_size_t size)
1014 struct pci_controller *hose = bus->uclass_priv;
1016 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1019 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1020 uint offset, ulong value,
1021 enum pci_size_t size)
1023 struct pci_controller *hose = bus->uclass_priv;
1025 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1028 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1030 struct udevice *dev;
1034 * Scan through all the PCI controllers. On x86 there will only be one
1035 * but that is not necessarily true on other hardware.
1038 device_find_first_child(bus, &dev);
1043 ret = uclass_next_device(&bus);
1051 int pci_find_next_device(struct udevice **devp)
1053 struct udevice *child = *devp;
1054 struct udevice *bus = child->parent;
1057 /* First try all the siblings */
1060 device_find_next_child(&child);
1067 /* We ran out of siblings. Try the next bus */
1068 ret = uclass_next_device(&bus);
1072 return bus ? skip_to_next_device(bus, devp) : 0;
1075 int pci_find_first_device(struct udevice **devp)
1077 struct udevice *bus;
1081 ret = uclass_first_device(UCLASS_PCI, &bus);
1085 return skip_to_next_device(bus, devp);
1088 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1092 return (value >> ((offset & 3) * 8)) & 0xff;
1094 return (value >> ((offset & 2) * 8)) & 0xffff;
1100 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1101 enum pci_size_t size)
1104 uint val_mask, shift;
1119 shift = (offset & off_mask) * 8;
1120 ldata = (value & val_mask) << shift;
1121 mask = val_mask << shift;
1122 value = (old & ~mask) | ldata;
1127 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1128 struct pci_region **memp, struct pci_region **prefp)
1130 struct udevice *bus = pci_get_controller(dev);
1131 struct pci_controller *hose = dev_get_uclass_priv(bus);
1137 for (i = 0; i < hose->region_count; i++) {
1138 switch (hose->regions[i].flags) {
1140 if (!*iop || (*iop)->size < hose->regions[i].size)
1141 *iop = hose->regions + i;
1143 case PCI_REGION_MEM:
1144 if (!*memp || (*memp)->size < hose->regions[i].size)
1145 *memp = hose->regions + i;
1147 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1148 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1149 *prefp = hose->regions + i;
1154 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1157 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1162 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1163 dm_pci_read_config32(dev, bar, &addr);
1164 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1165 return addr & PCI_BASE_ADDRESS_IO_MASK;
1167 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1170 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1174 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1175 dm_pci_write_config32(dev, bar, addr);
1178 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1179 pci_addr_t bus_addr, unsigned long flags,
1180 unsigned long skip_mask, phys_addr_t *pa)
1182 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1183 struct pci_region *res;
1186 if (hose->region_count == 0) {
1191 for (i = 0; i < hose->region_count; i++) {
1192 res = &hose->regions[i];
1194 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1197 if (res->flags & skip_mask)
1200 if (bus_addr >= res->bus_start &&
1201 (bus_addr - res->bus_start) < res->size) {
1202 *pa = (bus_addr - res->bus_start + res->phys_start);
1210 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1211 unsigned long flags)
1213 phys_addr_t phys_addr = 0;
1214 struct udevice *ctlr;
1217 /* The root controller has the region information */
1218 ctlr = pci_get_controller(dev);
1221 * if PCI_REGION_MEM is set we do a two pass search with preference
1222 * on matches that don't have PCI_REGION_SYS_MEMORY set
1224 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1225 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1226 flags, PCI_REGION_SYS_MEMORY,
1232 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1235 puts("pci_hose_bus_to_phys: invalid physical address\n");
1240 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1241 unsigned long flags, unsigned long skip_mask,
1244 struct pci_region *res;
1245 struct udevice *ctlr;
1246 pci_addr_t bus_addr;
1248 struct pci_controller *hose;
1250 /* The root controller has the region information */
1251 ctlr = pci_get_controller(dev);
1252 hose = dev_get_uclass_priv(ctlr);
1254 if (hose->region_count == 0) {
1259 for (i = 0; i < hose->region_count; i++) {
1260 res = &hose->regions[i];
1262 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1265 if (res->flags & skip_mask)
1268 bus_addr = phys_addr - res->phys_start + res->bus_start;
1270 if (bus_addr >= res->bus_start &&
1271 (bus_addr - res->bus_start) < res->size) {
1280 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1281 unsigned long flags)
1283 pci_addr_t bus_addr = 0;
1287 * if PCI_REGION_MEM is set we do a two pass search with preference
1288 * on matches that don't have PCI_REGION_SYS_MEMORY set
1290 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1291 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1292 PCI_REGION_SYS_MEMORY, &bus_addr);
1297 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1300 puts("pci_hose_phys_to_bus: invalid physical address\n");
1305 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1307 pci_addr_t pci_bus_addr;
1310 /* read BAR address */
1311 dm_pci_read_config32(dev, bar, &bar_response);
1312 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1315 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1316 * isn't actualy used on any platform because u-boot assumes a static
1317 * linear mapping. In the future, this could read the BAR size
1318 * and pass that as the size if needed.
1320 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1323 int dm_pci_find_capability(struct udevice *dev, int cap)
1327 int ttl = PCI_FIND_CAP_TTL;
1332 dm_pci_read_config16(dev, PCI_STATUS, &status);
1333 if (!(status & PCI_STATUS_CAP_LIST))
1336 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1337 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1338 pos = PCI_CB_CAPABILITY_LIST;
1340 pos = PCI_CAPABILITY_LIST;
1342 dm_pci_read_config8(dev, pos, &pos);
1344 if (pos < PCI_STD_HEADER_SIZEOF)
1347 dm_pci_read_config16(dev, pos, &ent);
1360 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1364 int pos = PCI_CFG_SPACE_SIZE;
1366 /* minimum 8 bytes per capability */
1367 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1369 dm_pci_read_config32(dev, pos, &header);
1371 * If we have no capabilities, this is indicated by cap ID,
1372 * cap version and next pointer all being 0.
1378 if (PCI_EXT_CAP_ID(header) == cap)
1381 pos = PCI_EXT_CAP_NEXT(header);
1382 if (pos < PCI_CFG_SPACE_SIZE)
1385 dm_pci_read_config32(dev, pos, &header);
1391 UCLASS_DRIVER(pci) = {
1394 .flags = DM_UC_FLAG_SEQ_ALIAS,
1395 .post_bind = dm_scan_fdt_dev,
1396 .pre_probe = pci_uclass_pre_probe,
1397 .post_probe = pci_uclass_post_probe,
1398 .child_post_bind = pci_uclass_child_post_bind,
1399 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1400 .per_child_platdata_auto_alloc_size =
1401 sizeof(struct pci_child_platdata),
1404 static const struct dm_pci_ops pci_bridge_ops = {
1405 .read_config = pci_bridge_read_config,
1406 .write_config = pci_bridge_write_config,
1409 static const struct udevice_id pci_bridge_ids[] = {
1410 { .compatible = "pci-bridge" },
1414 U_BOOT_DRIVER(pci_bridge_drv) = {
1415 .name = "pci_bridge_drv",
1417 .of_match = pci_bridge_ids,
1418 .ops = &pci_bridge_ops,
1421 UCLASS_DRIVER(pci_generic) = {
1422 .id = UCLASS_PCI_GENERIC,
1423 .name = "pci_generic",
1426 static const struct udevice_id pci_generic_ids[] = {
1427 { .compatible = "pci-generic" },
1431 U_BOOT_DRIVER(pci_generic_drv) = {
1432 .name = "pci_generic_drv",
1433 .id = UCLASS_PCI_GENERIC,
1434 .of_match = pci_generic_ids,
1439 struct udevice *bus;
1442 * Enumerate all known controller devices. Enumeration has the side-
1443 * effect of probing them, so PCIe devices will be enumerated too.
1445 for (uclass_first_device(UCLASS_PCI, &bus);
1447 uclass_next_device(&bus)) {