1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RCar Gen3 PCIEC driver
5 * Copyright (C) 2018-2019 Marek Vasut <marek.vasut@gmail.com>
7 * Based on Linux PCIe driver for Renesas R-Car SoCs
8 * Copyright (C) 2014 Renesas Electronics Europe Ltd
11 * arch/sh/drivers/pci/pcie-sh7786.c
12 * arch/sh/drivers/pci/ops-sh7786.c
13 * Copyright (C) 2009 - 2011 Paul Mundt
15 * Author: Phil Edworthy <phil.edworthy@renesas.com>
26 #define PCIECAR 0x000010
27 #define PCIECCTLR 0x000018
28 #define CONFIG_SEND_ENABLE BIT(31)
29 #define TYPE0 (0 << 8)
31 #define PCIECDR 0x000020
32 #define PCIEMSR 0x000028
33 #define PCIEINTXR 0x000400
34 #define PCIEPHYSR 0x0007f0
36 #define PCIEMSITXR 0x000840
38 /* Transfer control */
39 #define PCIETCTLR 0x02000
41 #define PCIETSTR 0x02004
42 #define DATA_LINK_ACTIVE 1
43 #define PCIEERRFR 0x02020
44 #define UNSUPPORTED_REQUEST BIT(4)
45 #define PCIEMSIFR 0x02044
46 #define PCIEMSIALR 0x02048
48 #define PCIEMSIAUR 0x0204c
49 #define PCIEMSIIER 0x02050
51 /* root port address */
52 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
54 /* local address reg & mask */
55 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
56 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
57 #define LAM_PREFETCH BIT(3)
58 #define LAM_64BIT BIT(2)
59 #define LAR_ENABLE BIT(1)
61 /* PCIe address reg & mask */
62 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
63 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
64 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
65 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
66 #define PAR_ENABLE BIT(31)
67 #define IO_SPACE BIT(8)
70 #define PCICONF(x) (0x010000 + ((x) * 0x4))
71 #define PMCAP(x) (0x010040 + ((x) * 0x4))
72 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
73 #define VCCAP(x) (0x010100 + ((x) * 0x4))
76 #define IDSETR1 0x011004
77 #define TLCTLR 0x011048
78 #define MACSR 0x011054
79 #define SPCHGFIN BIT(4)
80 #define SPCHGFAIL BIT(6)
81 #define SPCHGSUC BIT(7)
82 #define LINK_SPEED (0xf << 16)
83 #define LINK_SPEED_2_5GTS (1 << 16)
84 #define LINK_SPEED_5_0GTS (2 << 16)
85 #define MACCTLR 0x011058
86 #define SPEED_CHANGE BIT(24)
87 #define SCRAMBLE_DISABLE BIT(27)
88 #define MACS2R 0x011078
89 #define MACCGSPSETR 0x011084
90 #define SPCNGRSN BIT(31)
93 #define H1_PCIEPHYADRR 0x04000c
94 #define WRITE_CMD BIT(16)
95 #define PHY_ACK BIT(24)
99 #define H1_PCIEPHYDOUTR 0x040014
102 #define GEN2_PCIEPHYADDR 0x780
103 #define GEN2_PCIEPHYDATA 0x784
104 #define GEN2_PCIEPHYCTRL 0x78c
106 #define INT_PCI_MSI_NR 32
108 #define RCONF(x) (PCICONF(0) + (x))
109 #define RPMCAP(x) (PMCAP(0) + (x))
110 #define REXPCAP(x) (EXPCAP(0) + (x))
111 #define RVCCAP(x) (VCCAP(0) + (x))
113 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
114 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
115 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
117 #define RCAR_PCI_MAX_RESOURCES 4
118 #define MAX_NR_INBOUND_MAPS 6
120 #define PCI_EXP_FLAGS 2 /* Capabilities register */
121 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
122 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
123 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
124 #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
125 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
126 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
129 RCAR_PCI_ACCESS_READ,
130 RCAR_PCI_ACCESS_WRITE,
133 struct rcar_gen3_pcie_priv {
137 static void rcar_rmw32(struct udevice *dev, int where, u32 mask, u32 data)
139 struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
140 int shift = 8 * (where & 3);
142 clrsetbits_le32(priv->regs + (where & ~3),
143 mask << shift, data << shift);
146 static u32 rcar_read_conf(struct udevice *dev, int where)
148 struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
149 int shift = 8 * (where & 3);
151 return readl(priv->regs + (where & ~3)) >> shift;
154 static int rcar_pcie_config_access(struct udevice *udev,
155 unsigned char access_type,
156 pci_dev_t bdf, int where, ulong *data)
158 struct rcar_gen3_pcie_priv *priv = dev_get_platdata(udev);
159 u32 reg = where & ~3;
162 clrbits_le32(priv->regs + PCIEERRFR, 0);
164 /* Set the PIO address */
165 writel((bdf << 8) | reg, priv->regs + PCIECAR);
167 /* Enable the configuration access */
169 writel(CONFIG_SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR);
171 writel(CONFIG_SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR);
173 /* Check for errors */
174 if (readl(priv->regs + PCIEERRFR) & UNSUPPORTED_REQUEST)
177 /* Check for master and target aborts */
178 if (rcar_read_conf(udev, RCONF(PCI_STATUS)) &
179 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
182 if (access_type == RCAR_PCI_ACCESS_READ)
183 *data = readl(priv->regs + PCIECDR);
185 writel(*data, priv->regs + PCIECDR);
187 /* Disable the configuration access */
188 writel(0, priv->regs + PCIECCTLR);
193 static int rcar_gen3_pcie_addr_valid(pci_dev_t d, uint where)
207 static int rcar_gen3_pcie_read_config(struct udevice *dev, pci_dev_t bdf,
208 uint where, ulong *val,
209 enum pci_size_t size)
214 ret = rcar_gen3_pcie_addr_valid(bdf, where);
216 *val = pci_get_ff(size);
220 ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_READ,
225 *val = pci_conv_32_to_size(reg, where, size);
230 static int rcar_gen3_pcie_write_config(struct udevice *dev, pci_dev_t bdf,
231 uint where, ulong val,
232 enum pci_size_t size)
237 ret = rcar_gen3_pcie_addr_valid(bdf, where);
241 data = pci_conv_32_to_size(val, where, size);
243 ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_WRITE,
249 static int rcar_gen3_pcie_wait_for_phyrdy(struct udevice *dev)
251 struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
253 return wait_for_bit_le32((void *)priv->regs + PCIEPHYSR, PHYRDY,
257 static int rcar_gen3_pcie_wait_for_dl(struct udevice *dev)
259 struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
261 return wait_for_bit_le32((void *)priv->regs + PCIETSTR,
262 DATA_LINK_ACTIVE, true, 50, false);
265 static int rcar_gen3_pcie_hw_init(struct udevice *dev)
267 struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
270 /* Begin initialization */
271 writel(0, priv->regs + PCIETCTLR);
274 writel(1, priv->regs + PCIEMSR);
276 ret = rcar_gen3_pcie_wait_for_phyrdy(dev);
281 * Initial header for port config space is type 1, set the device
282 * class to match. Hardware takes care of propagating the IDSETR
283 * settings, so there is no need to bother with a quirk.
285 writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1);
288 * Setup Secondary Bus Number & Subordinate Bus Number, even though
289 * they aren't used, to avoid bridge being detected as broken.
291 rcar_rmw32(dev, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
292 rcar_rmw32(dev, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
294 /* Initialize default capabilities. */
295 rcar_rmw32(dev, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
296 rcar_rmw32(dev, REXPCAP(PCI_EXP_FLAGS),
297 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
298 rcar_rmw32(dev, RCONF(PCI_HEADER_TYPE), 0x7f,
299 PCI_HEADER_TYPE_BRIDGE);
301 /* Enable data link layer active state reporting */
302 rcar_rmw32(dev, REXPCAP(PCI_EXP_LNKCAP),
303 PCI_EXP_LNKCAP_DLLLARC, PCI_EXP_LNKCAP_DLLLARC);
305 /* Write out the physical slot number = 0 */
306 rcar_rmw32(dev, REXPCAP(PCI_EXP_SLTCAP),
307 PCI_EXP_SLTCAP_PSN, 0);
309 /* Set the completion timer timeout to the maximum 50ms. */
310 rcar_rmw32(dev, TLCTLR + 1, 0x3f, 50);
312 /* Terminate list of capabilities (Next Capability Offset=0) */
313 rcar_rmw32(dev, RVCCAP(0), 0xfff00000, 0);
315 /* Finish initialization - establish a PCI Express link */
316 writel(CFINIT, priv->regs + PCIETCTLR);
318 return rcar_gen3_pcie_wait_for_dl(dev);
321 static int rcar_gen3_pcie_probe(struct udevice *dev)
323 struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
324 struct pci_controller *hose = dev_get_uclass_priv(dev);
329 ret = clk_get_by_index(dev, 0, &pci_clk);
333 ret = clk_enable(&pci_clk);
337 for (i = 0; i < hose->region_count; i++) {
338 if (hose->regions[i].flags != PCI_REGION_SYS_MEMORY)
341 if (hose->regions[i].phys_start == 0)
344 mask = (hose->regions[i].size - 1) & ~0xf;
346 writel(hose->regions[i].phys_start, priv->regs + PCIEPRAR(0));
347 writel(hose->regions[i].phys_start, priv->regs + PCIELAR(0));
348 writel(mask, priv->regs + PCIELAMR(0));
352 writel(0, priv->regs + PCIEPRAR(4));
353 writel(0, priv->regs + PCIELAR(4));
354 writel(0, priv->regs + PCIELAMR(4));
356 ret = rcar_gen3_pcie_hw_init(dev);
360 for (i = 0, cnt = 0; i < hose->region_count; i++) {
361 if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
364 writel(0, priv->regs + PCIEPTCTLR(cnt));
365 writel((hose->regions[i].size - 1) & ~0x7f,
366 priv->regs + PCIEPAMR(cnt));
367 writel(upper_32_bits(hose->regions[i].phys_start),
368 priv->regs + PCIEPAUR(cnt));
369 writel(lower_32_bits(hose->regions[i].phys_start),
370 priv->regs + PCIEPALR(cnt));
372 if (hose->regions[i].flags == PCI_REGION_IO)
374 writel(mask, priv->regs + PCIEPTCTLR(cnt));
382 static int rcar_gen3_pcie_ofdata_to_platdata(struct udevice *dev)
384 struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
386 priv->regs = devfdt_get_addr_index(dev, 0);
393 static const struct dm_pci_ops rcar_gen3_pcie_ops = {
394 .read_config = rcar_gen3_pcie_read_config,
395 .write_config = rcar_gen3_pcie_write_config,
398 static const struct udevice_id rcar_gen3_pcie_ids[] = {
399 { .compatible = "renesas,pcie-rcar-gen3" },
403 U_BOOT_DRIVER(rcar_gen3_pcie) = {
404 .name = "rcar_gen3_pcie",
406 .of_match = rcar_gen3_pcie_ids,
407 .ops = &rcar_gen3_pcie_ops,
408 .probe = rcar_gen3_pcie_probe,
409 .ofdata_to_platdata = rcar_gen3_pcie_ofdata_to_platdata,
410 .platdata_auto_alloc_size = sizeof(struct rcar_gen3_pcie_priv),