2 * ***************************************************************************
3 * Copyright (C) 2015 Marvell International Ltd.
4 * ***************************************************************************
5 * This program is free software: you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation, either version 2 of the License, or any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * ***************************************************************************
20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
22 * Author: Victor Gu <xigu@marvell.com>
23 * Hezi Shahmoon <hezi.shahmoon@marvell.com>
31 #include <asm-generic/gpio.h>
32 #include <dm/device_compat.h>
33 #include <linux/ioport.h>
35 /* PCIe core registers */
36 #define PCIE_CORE_CMD_STATUS_REG 0x4
37 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
38 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
39 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
40 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
41 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
42 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
43 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
44 #define PCIE_CORE_LINK_TRAINING BIT(5)
45 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
46 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
47 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
48 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
49 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
51 /* PIO registers base address and register offsets */
52 #define PIO_BASE_ADDR 0x4000
53 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
54 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
55 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
56 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
57 #define PIO_COMPLETION_STATUS_SHIFT 7
58 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
59 #define PIO_COMPLETION_STATUS_OK 0
60 #define PIO_COMPLETION_STATUS_UR 1
61 #define PIO_COMPLETION_STATUS_CRS 2
62 #define PIO_COMPLETION_STATUS_CA 4
63 #define PIO_NON_POSTED_REQ BIT(10)
64 #define PIO_ERR_STATUS BIT(11)
65 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
66 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
67 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
68 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
69 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
70 #define PIO_START (PIO_BASE_ADDR + 0x1c)
71 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
73 /* Aardvark Control registers */
74 #define CONTROL_BASE_ADDR 0x4800
75 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
76 #define PCIE_GEN_SEL_MSK 0x3
77 #define PCIE_GEN_SEL_SHIFT 0x0
83 #define LANE_CNT_MSK 0x18
84 #define LANE_CNT_SHIFT 0x3
85 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
86 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
87 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
88 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
89 #define LINK_TRAINING_EN BIT(6)
90 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
91 #define PCIE_CORE_CTRL2_RESERVED 0x7
92 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
93 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
94 #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
96 /* LMI registers base address and register offsets */
97 #define LMI_BASE_ADDR 0x6000
98 #define CFG_REG (LMI_BASE_ADDR + 0x0)
99 #define LTSSM_SHIFT 24
100 #define LTSSM_MASK 0x3f
101 #define LTSSM_L0 0x10
103 /* PCIe core controller registers */
104 #define CTRL_CORE_BASE_ADDR 0x18000
105 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
106 #define CTRL_MODE_SHIFT 0x0
107 #define CTRL_MODE_MASK 0x1
108 #define PCIE_CORE_MODE_DIRECT 0x0
109 #define PCIE_CORE_MODE_COMMAND 0x1
111 /* Transaction types */
112 #define PCIE_CONFIG_RD_TYPE0 0x8
113 #define PCIE_CONFIG_RD_TYPE1 0x9
114 #define PCIE_CONFIG_WR_TYPE0 0xa
115 #define PCIE_CONFIG_WR_TYPE1 0xb
117 /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
118 #define PCIE_BDF(dev) (dev << 4)
119 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
120 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
121 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
122 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
123 #define PCIE_CONF_ADDR(bus, devfn, where) \
124 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
125 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
127 /* PCIe Retries & Timeout definitions */
128 #define MAX_RETRIES 10
129 #define PIO_WAIT_TIMEOUT 100
130 #define LINK_WAIT_TIMEOUT 100000
132 #define CFG_RD_UR_VAL 0xFFFFFFFF
133 #define CFG_RD_CRS_VAL 0xFFFF0001
136 * struct pcie_advk - Advk PCIe controller state
138 * @reg_base: The base address of the register space.
139 * @first_busno: This driver supports multiple PCIe controllers.
140 * first_busno stores the bus number of the PCIe root-port
141 * number which may vary depending on the PCIe setup
142 * (PEX switches etc).
143 * @device: The pointer to PCI uclass device.
151 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
153 writel(val, pcie->base + reg);
156 static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
158 return readl(pcie->base + reg);
162 * pcie_advk_addr_valid() - Check for valid bus address
164 * @bdf: The PCI device to access
165 * @first_busno: Bus number of the PCIe controller root complex
167 * Return: 1 on valid, 0 on invalid
169 static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
172 * In PCIE-E only a single device (0) can exist
173 * on the local bus. Beyound the local bus, there might be
174 * a Switch and everything is possible.
176 if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
183 * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
185 * @pcie: The PCI device to access
187 * Wait up to 1 micro second for PIO access to be accomplished.
189 * Return 1 (true) if PIO access is accomplished.
190 * Return 0 (false) if PIO access is timed out.
192 static int pcie_advk_wait_pio(struct pcie_advk *pcie)
197 for (count = 0; count < MAX_RETRIES; count++) {
198 start = advk_readl(pcie, PIO_START);
199 isr = advk_readl(pcie, PIO_ISR);
203 * Do not check the PIO state too frequently,
204 * 100us delay is appropriate.
206 udelay(PIO_WAIT_TIMEOUT);
209 dev_err(pcie->dev, "config read/write timed out\n");
214 * pcie_advk_check_pio_status() - Validate PIO status and get the read result
216 * @pcie: Pointer to the PCI bus
217 * @read: Read from or write to configuration space - true(read) false(write)
218 * @read_val: Pointer to the read result, only valid when read is true
221 static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
227 char *strcomp_status, *str_posted;
229 reg = advk_readl(pcie, PIO_STAT);
230 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
231 PIO_COMPLETION_STATUS_SHIFT;
234 case PIO_COMPLETION_STATUS_OK:
235 if (reg & PIO_ERR_STATUS) {
236 strcomp_status = "COMP_ERR";
239 /* Get the read result */
241 *read_val = advk_readl(pcie, PIO_RD_DATA);
243 strcomp_status = NULL;
245 case PIO_COMPLETION_STATUS_UR:
247 /* For reading, UR is not an error status. */
248 *read_val = CFG_RD_UR_VAL;
249 strcomp_status = NULL;
251 strcomp_status = "UR";
254 case PIO_COMPLETION_STATUS_CRS:
256 /* For reading, CRS is not an error status. */
257 *read_val = CFG_RD_CRS_VAL;
258 strcomp_status = NULL;
260 strcomp_status = "CRS";
263 case PIO_COMPLETION_STATUS_CA:
264 strcomp_status = "CA";
267 strcomp_status = "Unknown";
274 if (reg & PIO_NON_POSTED_REQ)
275 str_posted = "Non-posted";
277 str_posted = "Posted";
279 dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
280 str_posted, strcomp_status, reg,
281 advk_readl(pcie, PIO_ADDR_LS));
287 * pcie_advk_read_config() - Read from configuration space
289 * @bus: Pointer to the PCI bus
290 * @bdf: Identifies the PCIe device to access
291 * @offset: The offset into the device's configuration space
292 * @valuep: A pointer at which to store the read value
293 * @size: Indicates the size of access to perform
295 * Read a value of size @size from offset @offset within the configuration
296 * space of the device identified by the bus, device & function numbers in @bdf
297 * on the PCI bus @bus.
299 * Return: 0 on success
301 static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
302 uint offset, ulong *valuep,
303 enum pci_size_t size)
305 struct pcie_advk *pcie = dev_get_priv(bus);
309 dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
310 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
312 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
313 dev_dbg(pcie->dev, "- out of range\n");
314 *valuep = pci_get_ff(size);
319 advk_writel(pcie, 0, PIO_START);
320 advk_writel(pcie, 1, PIO_ISR);
322 /* Program the control register */
323 reg = advk_readl(pcie, PIO_CTRL);
324 reg &= ~PIO_CTRL_TYPE_MASK;
325 if (PCI_BUS(bdf) == pcie->first_busno)
326 reg |= PCIE_CONFIG_RD_TYPE0;
328 reg |= PCIE_CONFIG_RD_TYPE1;
329 advk_writel(pcie, reg, PIO_CTRL);
331 /* Program the address registers */
332 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
333 advk_writel(pcie, reg, PIO_ADDR_LS);
334 advk_writel(pcie, 0, PIO_ADDR_MS);
336 /* Start the transfer */
337 advk_writel(pcie, 1, PIO_START);
339 if (!pcie_advk_wait_pio(pcie))
342 /* Check PIO status and get the read result */
343 ret = pcie_advk_check_pio_status(pcie, true, ®);
347 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
349 *valuep = pci_conv_32_to_size(reg, offset, size);
355 * pcie_calc_datastrobe() - Calculate data strobe
357 * @offset: The offset into the device's configuration space
358 * @size: Indicates the size of access to perform
360 * Calculate data strobe according to offset and size
363 static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
365 uint bytes, data_strobe;
378 data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
384 * pcie_advk_write_config() - Write to configuration space
386 * @bus: Pointer to the PCI bus
387 * @bdf: Identifies the PCIe device to access
388 * @offset: The offset into the device's configuration space
389 * @value: The value to write
390 * @size: Indicates the size of access to perform
392 * Write the value @value of size @size from offset @offset within the
393 * configuration space of the device identified by the bus, device & function
394 * numbers in @bdf on the PCI bus @bus.
396 * Return: 0 on success
398 static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
399 uint offset, ulong value,
400 enum pci_size_t size)
402 struct pcie_advk *pcie = dev_get_priv(bus);
405 dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
406 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
407 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
408 offset, size, value);
410 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
411 dev_dbg(pcie->dev, "- out of range\n");
416 advk_writel(pcie, 0, PIO_START);
417 advk_writel(pcie, 1, PIO_ISR);
419 /* Program the control register */
420 reg = advk_readl(pcie, PIO_CTRL);
421 reg &= ~PIO_CTRL_TYPE_MASK;
422 if (PCI_BUS(bdf) == pcie->first_busno)
423 reg |= PCIE_CONFIG_WR_TYPE0;
425 reg |= PCIE_CONFIG_WR_TYPE1;
426 advk_writel(pcie, reg, PIO_CTRL);
428 /* Program the address registers */
429 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
430 advk_writel(pcie, reg, PIO_ADDR_LS);
431 advk_writel(pcie, 0, PIO_ADDR_MS);
432 dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
434 /* Program the data register */
435 reg = pci_conv_size_to_32(0, value, offset, size);
436 advk_writel(pcie, reg, PIO_WR_DATA);
437 dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
439 /* Program the data strobe */
440 reg = pcie_calc_datastrobe(offset, size);
441 advk_writel(pcie, reg, PIO_WR_DATA_STRB);
442 dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
444 /* Start the transfer */
445 advk_writel(pcie, 1, PIO_START);
447 if (!pcie_advk_wait_pio(pcie)) {
448 dev_dbg(pcie->dev, "- wait pio timeout\n");
452 /* Check PIO status */
453 pcie_advk_check_pio_status(pcie, false, ®);
459 * pcie_advk_link_up() - Check if PCIe link is up or not
461 * @pcie: The PCI device to access
463 * Return 1 (true) on link up.
464 * Return 0 (false) on link down.
466 static int pcie_advk_link_up(struct pcie_advk *pcie)
468 u32 val, ltssm_state;
470 val = advk_readl(pcie, CFG_REG);
471 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
472 return ltssm_state >= LTSSM_L0;
476 * pcie_advk_wait_for_link() - Wait for link training to be accomplished
478 * @pcie: The PCI device to access
480 * Wait up to 1 second for link training to be accomplished.
482 * Return 1 (true) if link training ends up with link up success.
483 * Return 0 (false) if link training ends up with link up failure.
485 static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
489 /* check if the link is up or not */
490 for (retries = 0; retries < MAX_RETRIES; retries++) {
491 if (pcie_advk_link_up(pcie)) {
492 printf("PCIE-%d: Link up\n", pcie->first_busno);
496 udelay(LINK_WAIT_TIMEOUT);
499 printf("PCIE-%d: Link down\n", pcie->first_busno);
505 * pcie_advk_setup_hw() - PCIe initailzation
507 * @pcie: The PCI device to access
509 * Return: 0 on success
511 static int pcie_advk_setup_hw(struct pcie_advk *pcie)
515 /* Set to Direct mode */
516 reg = advk_readl(pcie, CTRL_CONFIG_REG);
517 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
518 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
519 advk_writel(pcie, reg, CTRL_CONFIG_REG);
521 /* Set PCI global control register to RC mode */
522 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
523 reg |= (IS_RC_MSK << IS_RC_SHIFT);
524 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
526 /* Set Advanced Error Capabilities and Control PF0 register */
527 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
528 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
529 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
530 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
531 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
533 /* Set PCIe Device Control and Status 1 PF0 register */
534 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
535 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
536 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
538 /* Program PCIe Control 2 to disable strict ordering */
539 reg = PCIE_CORE_CTRL2_RESERVED |
540 PCIE_CORE_CTRL2_TD_ENABLE;
541 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
544 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
545 reg &= ~PCIE_GEN_SEL_MSK;
547 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
550 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
551 reg &= ~LANE_CNT_MSK;
553 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
555 /* Enable link training */
556 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
557 reg |= LINK_TRAINING_EN;
558 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
561 * Enable AXI address window location generation:
562 * When it is enabled, the default outbound window
563 * configurations (Default User Field: 0xD0074CFC)
564 * are used to transparent address translation for
565 * the outbound transactions. Thus, PCIe address
566 * windows are not required.
568 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
569 reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
570 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
573 * Bypass the address window mapping for PIO:
574 * Since PIO access already contains all required
575 * info over AXI interface by PIO registers, the
576 * address window is not required.
578 reg = advk_readl(pcie, PIO_CTRL);
579 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
580 advk_writel(pcie, reg, PIO_CTRL);
582 /* Start link training */
583 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
584 reg |= PCIE_CORE_LINK_TRAINING;
585 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
587 /* Wait for PCIe link up */
588 if (pcie_advk_wait_for_link(pcie))
591 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
592 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
593 PCIE_CORE_CMD_IO_ACCESS_EN |
594 PCIE_CORE_CMD_MEM_IO_REQ_EN;
595 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
601 * pcie_advk_probe() - Probe the PCIe bus for active link
603 * @dev: A pointer to the device being operated on
605 * Probe for an active link on the PCIe bus and configure the controller
606 * to enable this port.
608 * Return: 0 on success, else -ENODEV
610 static int pcie_advk_probe(struct udevice *dev)
612 struct pcie_advk *pcie = dev_get_priv(dev);
614 #if CONFIG_IS_ENABLED(DM_GPIO)
615 struct gpio_desc reset_gpio;
617 gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
620 * Issue reset to add-in card through the dedicated GPIO.
621 * Some boards are connecting the card reset pin to common system
622 * reset wire and others are using separate GPIO port.
623 * In the last case we have to release a reset of the addon card
627 * The PCIe RESET signal is not supposed to be released along
628 * with the SOC RESET signal. It should be lowered as early as
629 * possible before PCIe PHY initialization. Moreover, the PCIe
630 * clock should be gated as well.
632 if (dm_gpio_is_valid(&reset_gpio)) {
633 dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
634 dm_gpio_set_value(&reset_gpio, 0);
636 dm_gpio_set_value(&reset_gpio, 1);
639 dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
642 pcie->first_busno = dev->seq;
643 pcie->dev = pci_get_controller(dev);
645 return pcie_advk_setup_hw(pcie);
649 * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
651 * @dev: A pointer to the device being operated on
653 * Translate relevant data from the device tree pertaining to device @dev into
654 * state that the driver will later make use of. This state is stored in the
655 * device's private data structure.
657 * Return: 0 on success, else -EINVAL
659 static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
661 struct pcie_advk *pcie = dev_get_priv(dev);
663 /* Get the register base address */
664 pcie->base = (void *)dev_read_addr_index(dev, 0);
665 if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
671 static const struct dm_pci_ops pcie_advk_ops = {
672 .read_config = pcie_advk_read_config,
673 .write_config = pcie_advk_write_config,
676 static const struct udevice_id pcie_advk_ids[] = {
677 { .compatible = "marvell,armada-37xx-pcie" },
681 U_BOOT_DRIVER(pcie_advk) = {
684 .of_match = pcie_advk_ids,
685 .ops = &pcie_advk_ops,
686 .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
687 .probe = pcie_advk_probe,
688 .priv_auto_alloc_size = sizeof(struct pcie_advk),