2 * ***************************************************************************
3 * Copyright (C) 2015 Marvell International Ltd.
4 * ***************************************************************************
5 * This program is free software: you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation, either version 2 of the License, or any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * ***************************************************************************
20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
22 * Author: Victor Gu <xigu@marvell.com>
23 * Hezi Shahmoon <hezi.shahmoon@marvell.com>
31 #include <asm-generic/gpio.h>
32 #include <dm/device_compat.h>
33 #include <linux/bitops.h>
34 #include <linux/delay.h>
35 #include <linux/ioport.h>
37 /* PCIe core registers */
38 #define PCIE_CORE_CMD_STATUS_REG 0x4
39 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
40 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
41 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
42 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
43 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
44 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
45 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
46 #define PCIE_CORE_LINK_TRAINING BIT(5)
47 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
48 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
49 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
50 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
51 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
53 /* PIO registers base address and register offsets */
54 #define PIO_BASE_ADDR 0x4000
55 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
56 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
57 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
58 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
59 #define PIO_COMPLETION_STATUS_SHIFT 7
60 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
61 #define PIO_COMPLETION_STATUS_OK 0
62 #define PIO_COMPLETION_STATUS_UR 1
63 #define PIO_COMPLETION_STATUS_CRS 2
64 #define PIO_COMPLETION_STATUS_CA 4
65 #define PIO_NON_POSTED_REQ BIT(10)
66 #define PIO_ERR_STATUS BIT(11)
67 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
68 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
69 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
70 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
71 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
72 #define PIO_START (PIO_BASE_ADDR + 0x1c)
73 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
75 /* Aardvark Control registers */
76 #define CONTROL_BASE_ADDR 0x4800
77 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
78 #define PCIE_GEN_SEL_MSK 0x3
79 #define PCIE_GEN_SEL_SHIFT 0x0
85 #define LANE_CNT_MSK 0x18
86 #define LANE_CNT_SHIFT 0x3
87 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
88 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
89 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
90 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
91 #define LINK_TRAINING_EN BIT(6)
92 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
93 #define PCIE_CORE_CTRL2_RESERVED 0x7
94 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
95 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
96 #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
98 /* LMI registers base address and register offsets */
99 #define LMI_BASE_ADDR 0x6000
100 #define CFG_REG (LMI_BASE_ADDR + 0x0)
101 #define LTSSM_SHIFT 24
102 #define LTSSM_MASK 0x3f
103 #define LTSSM_L0 0x10
105 /* PCIe core controller registers */
106 #define CTRL_CORE_BASE_ADDR 0x18000
107 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
108 #define CTRL_MODE_SHIFT 0x0
109 #define CTRL_MODE_MASK 0x1
110 #define PCIE_CORE_MODE_DIRECT 0x0
111 #define PCIE_CORE_MODE_COMMAND 0x1
113 /* Transaction types */
114 #define PCIE_CONFIG_RD_TYPE0 0x8
115 #define PCIE_CONFIG_RD_TYPE1 0x9
116 #define PCIE_CONFIG_WR_TYPE0 0xa
117 #define PCIE_CONFIG_WR_TYPE1 0xb
119 /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
120 #define PCIE_BDF(dev) (dev << 4)
121 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
122 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
123 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
124 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
125 #define PCIE_CONF_ADDR(bus, devfn, where) \
126 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
127 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
129 /* PCIe Retries & Timeout definitions */
130 #define MAX_RETRIES 10
131 #define PIO_WAIT_TIMEOUT 100
132 #define LINK_WAIT_TIMEOUT 100000
134 #define CFG_RD_UR_VAL 0xFFFFFFFF
135 #define CFG_RD_CRS_VAL 0xFFFF0001
138 * struct pcie_advk - Advk PCIe controller state
140 * @reg_base: The base address of the register space.
141 * @first_busno: This driver supports multiple PCIe controllers.
142 * first_busno stores the bus number of the PCIe root-port
143 * number which may vary depending on the PCIe setup
144 * (PEX switches etc).
145 * @device: The pointer to PCI uclass device.
153 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
155 writel(val, pcie->base + reg);
158 static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
160 return readl(pcie->base + reg);
164 * pcie_advk_addr_valid() - Check for valid bus address
166 * @bdf: The PCI device to access
167 * @first_busno: Bus number of the PCIe controller root complex
169 * Return: 1 on valid, 0 on invalid
171 static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
174 * In PCIE-E only a single device (0) can exist
175 * on the local bus. Beyound the local bus, there might be
176 * a Switch and everything is possible.
178 if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
185 * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
187 * @pcie: The PCI device to access
189 * Wait up to 1 micro second for PIO access to be accomplished.
191 * Return 1 (true) if PIO access is accomplished.
192 * Return 0 (false) if PIO access is timed out.
194 static int pcie_advk_wait_pio(struct pcie_advk *pcie)
199 for (count = 0; count < MAX_RETRIES; count++) {
200 start = advk_readl(pcie, PIO_START);
201 isr = advk_readl(pcie, PIO_ISR);
205 * Do not check the PIO state too frequently,
206 * 100us delay is appropriate.
208 udelay(PIO_WAIT_TIMEOUT);
211 dev_err(pcie->dev, "config read/write timed out\n");
216 * pcie_advk_check_pio_status() - Validate PIO status and get the read result
218 * @pcie: Pointer to the PCI bus
219 * @read: Read from or write to configuration space - true(read) false(write)
220 * @read_val: Pointer to the read result, only valid when read is true
223 static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
229 char *strcomp_status, *str_posted;
231 reg = advk_readl(pcie, PIO_STAT);
232 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
233 PIO_COMPLETION_STATUS_SHIFT;
236 case PIO_COMPLETION_STATUS_OK:
237 if (reg & PIO_ERR_STATUS) {
238 strcomp_status = "COMP_ERR";
241 /* Get the read result */
243 *read_val = advk_readl(pcie, PIO_RD_DATA);
245 strcomp_status = NULL;
247 case PIO_COMPLETION_STATUS_UR:
249 /* For reading, UR is not an error status. */
250 *read_val = CFG_RD_UR_VAL;
251 strcomp_status = NULL;
253 strcomp_status = "UR";
256 case PIO_COMPLETION_STATUS_CRS:
258 /* For reading, CRS is not an error status. */
259 *read_val = CFG_RD_CRS_VAL;
260 strcomp_status = NULL;
262 strcomp_status = "CRS";
265 case PIO_COMPLETION_STATUS_CA:
266 strcomp_status = "CA";
269 strcomp_status = "Unknown";
276 if (reg & PIO_NON_POSTED_REQ)
277 str_posted = "Non-posted";
279 str_posted = "Posted";
281 dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
282 str_posted, strcomp_status, reg,
283 advk_readl(pcie, PIO_ADDR_LS));
289 * pcie_advk_read_config() - Read from configuration space
291 * @bus: Pointer to the PCI bus
292 * @bdf: Identifies the PCIe device to access
293 * @offset: The offset into the device's configuration space
294 * @valuep: A pointer at which to store the read value
295 * @size: Indicates the size of access to perform
297 * Read a value of size @size from offset @offset within the configuration
298 * space of the device identified by the bus, device & function numbers in @bdf
299 * on the PCI bus @bus.
301 * Return: 0 on success
303 static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
304 uint offset, ulong *valuep,
305 enum pci_size_t size)
307 struct pcie_advk *pcie = dev_get_priv(bus);
311 dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
312 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
314 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
315 dev_dbg(pcie->dev, "- out of range\n");
316 *valuep = pci_get_ff(size);
321 advk_writel(pcie, 0, PIO_START);
322 advk_writel(pcie, 1, PIO_ISR);
324 /* Program the control register */
325 reg = advk_readl(pcie, PIO_CTRL);
326 reg &= ~PIO_CTRL_TYPE_MASK;
327 if (PCI_BUS(bdf) == pcie->first_busno)
328 reg |= PCIE_CONFIG_RD_TYPE0;
330 reg |= PCIE_CONFIG_RD_TYPE1;
331 advk_writel(pcie, reg, PIO_CTRL);
333 /* Program the address registers */
334 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
335 advk_writel(pcie, reg, PIO_ADDR_LS);
336 advk_writel(pcie, 0, PIO_ADDR_MS);
338 /* Start the transfer */
339 advk_writel(pcie, 1, PIO_START);
341 if (!pcie_advk_wait_pio(pcie))
344 /* Check PIO status and get the read result */
345 ret = pcie_advk_check_pio_status(pcie, true, ®);
349 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
351 *valuep = pci_conv_32_to_size(reg, offset, size);
357 * pcie_calc_datastrobe() - Calculate data strobe
359 * @offset: The offset into the device's configuration space
360 * @size: Indicates the size of access to perform
362 * Calculate data strobe according to offset and size
365 static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
367 uint bytes, data_strobe;
380 data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
386 * pcie_advk_write_config() - Write to configuration space
388 * @bus: Pointer to the PCI bus
389 * @bdf: Identifies the PCIe device to access
390 * @offset: The offset into the device's configuration space
391 * @value: The value to write
392 * @size: Indicates the size of access to perform
394 * Write the value @value of size @size from offset @offset within the
395 * configuration space of the device identified by the bus, device & function
396 * numbers in @bdf on the PCI bus @bus.
398 * Return: 0 on success
400 static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
401 uint offset, ulong value,
402 enum pci_size_t size)
404 struct pcie_advk *pcie = dev_get_priv(bus);
407 dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
408 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
409 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
410 offset, size, value);
412 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
413 dev_dbg(pcie->dev, "- out of range\n");
418 advk_writel(pcie, 0, PIO_START);
419 advk_writel(pcie, 1, PIO_ISR);
421 /* Program the control register */
422 reg = advk_readl(pcie, PIO_CTRL);
423 reg &= ~PIO_CTRL_TYPE_MASK;
424 if (PCI_BUS(bdf) == pcie->first_busno)
425 reg |= PCIE_CONFIG_WR_TYPE0;
427 reg |= PCIE_CONFIG_WR_TYPE1;
428 advk_writel(pcie, reg, PIO_CTRL);
430 /* Program the address registers */
431 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
432 advk_writel(pcie, reg, PIO_ADDR_LS);
433 advk_writel(pcie, 0, PIO_ADDR_MS);
434 dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
436 /* Program the data register */
437 reg = pci_conv_size_to_32(0, value, offset, size);
438 advk_writel(pcie, reg, PIO_WR_DATA);
439 dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
441 /* Program the data strobe */
442 reg = pcie_calc_datastrobe(offset, size);
443 advk_writel(pcie, reg, PIO_WR_DATA_STRB);
444 dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
446 /* Start the transfer */
447 advk_writel(pcie, 1, PIO_START);
449 if (!pcie_advk_wait_pio(pcie)) {
450 dev_dbg(pcie->dev, "- wait pio timeout\n");
454 /* Check PIO status */
455 pcie_advk_check_pio_status(pcie, false, ®);
461 * pcie_advk_link_up() - Check if PCIe link is up or not
463 * @pcie: The PCI device to access
465 * Return 1 (true) on link up.
466 * Return 0 (false) on link down.
468 static int pcie_advk_link_up(struct pcie_advk *pcie)
470 u32 val, ltssm_state;
472 val = advk_readl(pcie, CFG_REG);
473 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
474 return ltssm_state >= LTSSM_L0;
478 * pcie_advk_wait_for_link() - Wait for link training to be accomplished
480 * @pcie: The PCI device to access
482 * Wait up to 1 second for link training to be accomplished.
484 * Return 1 (true) if link training ends up with link up success.
485 * Return 0 (false) if link training ends up with link up failure.
487 static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
491 /* check if the link is up or not */
492 for (retries = 0; retries < MAX_RETRIES; retries++) {
493 if (pcie_advk_link_up(pcie)) {
494 printf("PCIE-%d: Link up\n", pcie->first_busno);
498 udelay(LINK_WAIT_TIMEOUT);
501 printf("PCIE-%d: Link down\n", pcie->first_busno);
507 * pcie_advk_setup_hw() - PCIe initailzation
509 * @pcie: The PCI device to access
511 * Return: 0 on success
513 static int pcie_advk_setup_hw(struct pcie_advk *pcie)
517 /* Set to Direct mode */
518 reg = advk_readl(pcie, CTRL_CONFIG_REG);
519 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
520 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
521 advk_writel(pcie, reg, CTRL_CONFIG_REG);
523 /* Set PCI global control register to RC mode */
524 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
525 reg |= (IS_RC_MSK << IS_RC_SHIFT);
526 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
528 /* Set Advanced Error Capabilities and Control PF0 register */
529 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
530 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
531 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
532 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
533 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
535 /* Set PCIe Device Control and Status 1 PF0 register */
536 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
537 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
538 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
540 /* Program PCIe Control 2 to disable strict ordering */
541 reg = PCIE_CORE_CTRL2_RESERVED |
542 PCIE_CORE_CTRL2_TD_ENABLE;
543 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
546 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
547 reg &= ~PCIE_GEN_SEL_MSK;
549 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
552 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
553 reg &= ~LANE_CNT_MSK;
555 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
557 /* Enable link training */
558 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
559 reg |= LINK_TRAINING_EN;
560 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
563 * Enable AXI address window location generation:
564 * When it is enabled, the default outbound window
565 * configurations (Default User Field: 0xD0074CFC)
566 * are used to transparent address translation for
567 * the outbound transactions. Thus, PCIe address
568 * windows are not required.
570 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
571 reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
572 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
575 * Bypass the address window mapping for PIO:
576 * Since PIO access already contains all required
577 * info over AXI interface by PIO registers, the
578 * address window is not required.
580 reg = advk_readl(pcie, PIO_CTRL);
581 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
582 advk_writel(pcie, reg, PIO_CTRL);
584 /* Start link training */
585 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
586 reg |= PCIE_CORE_LINK_TRAINING;
587 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
589 /* Wait for PCIe link up */
590 if (pcie_advk_wait_for_link(pcie))
593 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
594 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
595 PCIE_CORE_CMD_IO_ACCESS_EN |
596 PCIE_CORE_CMD_MEM_IO_REQ_EN;
597 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
603 * pcie_advk_probe() - Probe the PCIe bus for active link
605 * @dev: A pointer to the device being operated on
607 * Probe for an active link on the PCIe bus and configure the controller
608 * to enable this port.
610 * Return: 0 on success, else -ENODEV
612 static int pcie_advk_probe(struct udevice *dev)
614 struct pcie_advk *pcie = dev_get_priv(dev);
616 #if CONFIG_IS_ENABLED(DM_GPIO)
617 struct gpio_desc reset_gpio;
619 gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
622 * Issue reset to add-in card through the dedicated GPIO.
623 * Some boards are connecting the card reset pin to common system
624 * reset wire and others are using separate GPIO port.
625 * In the last case we have to release a reset of the addon card
629 * The PCIe RESET signal is not supposed to be released along
630 * with the SOC RESET signal. It should be lowered as early as
631 * possible before PCIe PHY initialization. Moreover, the PCIe
632 * clock should be gated as well.
634 if (dm_gpio_is_valid(&reset_gpio)) {
635 dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
636 dm_gpio_set_value(&reset_gpio, 0);
638 dm_gpio_set_value(&reset_gpio, 1);
641 dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
644 pcie->first_busno = dev->seq;
645 pcie->dev = pci_get_controller(dev);
647 return pcie_advk_setup_hw(pcie);
651 * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
653 * @dev: A pointer to the device being operated on
655 * Translate relevant data from the device tree pertaining to device @dev into
656 * state that the driver will later make use of. This state is stored in the
657 * device's private data structure.
659 * Return: 0 on success, else -EINVAL
661 static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
663 struct pcie_advk *pcie = dev_get_priv(dev);
665 /* Get the register base address */
666 pcie->base = (void *)dev_read_addr_index(dev, 0);
667 if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
673 static const struct dm_pci_ops pcie_advk_ops = {
674 .read_config = pcie_advk_read_config,
675 .write_config = pcie_advk_write_config,
678 static const struct udevice_id pcie_advk_ids[] = {
679 { .compatible = "marvell,armada-37xx-pcie" },
683 U_BOOT_DRIVER(pcie_advk) = {
686 .of_match = pcie_advk_ids,
687 .ops = &pcie_advk_ops,
688 .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
689 .probe = pcie_advk_probe,
690 .priv_auto_alloc_size = sizeof(struct pcie_advk),