2 * ***************************************************************************
3 * Copyright (C) 2015 Marvell International Ltd.
4 * ***************************************************************************
5 * This program is free software: you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation, either version 2 of the License, or any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * ***************************************************************************
20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
22 * Author: Victor Gu <xigu@marvell.com>
23 * Hezi Shahmoon <hezi.shahmoon@marvell.com>
31 #include <asm-generic/gpio.h>
32 #include <linux/ioport.h>
34 /* PCIe core registers */
35 #define PCIE_CORE_CMD_STATUS_REG 0x4
36 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
37 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
38 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
39 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
40 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
41 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
42 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
43 #define PCIE_CORE_LINK_TRAINING BIT(5)
44 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
45 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
46 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
47 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
48 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
50 /* PIO registers base address and register offsets */
51 #define PIO_BASE_ADDR 0x4000
52 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
53 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
54 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
55 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
56 #define PIO_COMPLETION_STATUS_SHIFT 7
57 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
58 #define PIO_COMPLETION_STATUS_OK 0
59 #define PIO_COMPLETION_STATUS_UR 1
60 #define PIO_COMPLETION_STATUS_CRS 2
61 #define PIO_COMPLETION_STATUS_CA 4
62 #define PIO_NON_POSTED_REQ BIT(10)
63 #define PIO_ERR_STATUS BIT(11)
64 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
65 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
66 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
67 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
68 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
69 #define PIO_START (PIO_BASE_ADDR + 0x1c)
70 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
72 /* Aardvark Control registers */
73 #define CONTROL_BASE_ADDR 0x4800
74 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
75 #define PCIE_GEN_SEL_MSK 0x3
76 #define PCIE_GEN_SEL_SHIFT 0x0
82 #define LANE_CNT_MSK 0x18
83 #define LANE_CNT_SHIFT 0x3
84 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
85 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
86 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
87 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
88 #define LINK_TRAINING_EN BIT(6)
89 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
90 #define PCIE_CORE_CTRL2_RESERVED 0x7
91 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
92 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
93 #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
95 /* LMI registers base address and register offsets */
96 #define LMI_BASE_ADDR 0x6000
97 #define CFG_REG (LMI_BASE_ADDR + 0x0)
98 #define LTSSM_SHIFT 24
99 #define LTSSM_MASK 0x3f
100 #define LTSSM_L0 0x10
102 /* PCIe core controller registers */
103 #define CTRL_CORE_BASE_ADDR 0x18000
104 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
105 #define CTRL_MODE_SHIFT 0x0
106 #define CTRL_MODE_MASK 0x1
107 #define PCIE_CORE_MODE_DIRECT 0x0
108 #define PCIE_CORE_MODE_COMMAND 0x1
110 /* Transaction types */
111 #define PCIE_CONFIG_RD_TYPE0 0x8
112 #define PCIE_CONFIG_RD_TYPE1 0x9
113 #define PCIE_CONFIG_WR_TYPE0 0xa
114 #define PCIE_CONFIG_WR_TYPE1 0xb
116 /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
117 #define PCIE_BDF(dev) (dev << 4)
118 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
119 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
120 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
121 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
122 #define PCIE_CONF_ADDR(bus, devfn, where) \
123 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
124 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
126 /* PCIe Retries & Timeout definitions */
127 #define MAX_RETRIES 10
128 #define PIO_WAIT_TIMEOUT 100
129 #define LINK_WAIT_TIMEOUT 100000
131 #define CFG_RD_UR_VAL 0xFFFFFFFF
132 #define CFG_RD_CRS_VAL 0xFFFF0001
134 DECLARE_GLOBAL_DATA_PTR;
137 * struct pcie_advk - Advk PCIe controller state
139 * @reg_base: The base address of the register space.
140 * @first_busno: This driver supports multiple PCIe controllers.
141 * first_busno stores the bus number of the PCIe root-port
142 * number which may vary depending on the PCIe setup
143 * (PEX switches etc).
144 * @device: The pointer to PCI uclass device.
152 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
154 writel(val, pcie->base + reg);
157 static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
159 return readl(pcie->base + reg);
163 * pcie_advk_addr_valid() - Check for valid bus address
165 * @bdf: The PCI device to access
166 * @first_busno: Bus number of the PCIe controller root complex
168 * Return: 1 on valid, 0 on invalid
170 static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
173 * In PCIE-E only a single device (0) can exist
174 * on the local bus. Beyound the local bus, there might be
175 * a Switch and everything is possible.
177 if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
184 * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
186 * @pcie: The PCI device to access
188 * Wait up to 1 micro second for PIO access to be accomplished.
190 * Return 1 (true) if PIO access is accomplished.
191 * Return 0 (false) if PIO access is timed out.
193 static int pcie_advk_wait_pio(struct pcie_advk *pcie)
198 for (count = 0; count < MAX_RETRIES; count++) {
199 start = advk_readl(pcie, PIO_START);
200 isr = advk_readl(pcie, PIO_ISR);
204 * Do not check the PIO state too frequently,
205 * 100us delay is appropriate.
207 udelay(PIO_WAIT_TIMEOUT);
210 dev_err(pcie->dev, "config read/write timed out\n");
215 * pcie_advk_check_pio_status() - Validate PIO status and get the read result
217 * @pcie: Pointer to the PCI bus
218 * @read: Read from or write to configuration space - true(read) false(write)
219 * @read_val: Pointer to the read result, only valid when read is true
222 static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
228 char *strcomp_status, *str_posted;
230 reg = advk_readl(pcie, PIO_STAT);
231 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
232 PIO_COMPLETION_STATUS_SHIFT;
235 case PIO_COMPLETION_STATUS_OK:
236 if (reg & PIO_ERR_STATUS) {
237 strcomp_status = "COMP_ERR";
240 /* Get the read result */
242 *read_val = advk_readl(pcie, PIO_RD_DATA);
244 strcomp_status = NULL;
246 case PIO_COMPLETION_STATUS_UR:
248 /* For reading, UR is not an error status. */
249 *read_val = CFG_RD_UR_VAL;
250 strcomp_status = NULL;
252 strcomp_status = "UR";
255 case PIO_COMPLETION_STATUS_CRS:
257 /* For reading, CRS is not an error status. */
258 *read_val = CFG_RD_CRS_VAL;
259 strcomp_status = NULL;
261 strcomp_status = "CRS";
264 case PIO_COMPLETION_STATUS_CA:
265 strcomp_status = "CA";
268 strcomp_status = "Unknown";
275 if (reg & PIO_NON_POSTED_REQ)
276 str_posted = "Non-posted";
278 str_posted = "Posted";
280 dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
281 str_posted, strcomp_status, reg,
282 advk_readl(pcie, PIO_ADDR_LS));
288 * pcie_advk_read_config() - Read from configuration space
290 * @bus: Pointer to the PCI bus
291 * @bdf: Identifies the PCIe device to access
292 * @offset: The offset into the device's configuration space
293 * @valuep: A pointer at which to store the read value
294 * @size: Indicates the size of access to perform
296 * Read a value of size @size from offset @offset within the configuration
297 * space of the device identified by the bus, device & function numbers in @bdf
298 * on the PCI bus @bus.
300 * Return: 0 on success
302 static int pcie_advk_read_config(struct udevice *bus, pci_dev_t bdf,
303 uint offset, ulong *valuep,
304 enum pci_size_t size)
306 struct pcie_advk *pcie = dev_get_priv(bus);
310 dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
311 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
313 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
314 dev_dbg(pcie->dev, "- out of range\n");
315 *valuep = pci_get_ff(size);
320 advk_writel(pcie, 0, PIO_START);
321 advk_writel(pcie, 1, PIO_ISR);
323 /* Program the control register */
324 reg = advk_readl(pcie, PIO_CTRL);
325 reg &= ~PIO_CTRL_TYPE_MASK;
326 if (PCI_BUS(bdf) == pcie->first_busno)
327 reg |= PCIE_CONFIG_RD_TYPE0;
329 reg |= PCIE_CONFIG_RD_TYPE1;
330 advk_writel(pcie, reg, PIO_CTRL);
332 /* Program the address registers */
333 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
334 advk_writel(pcie, reg, PIO_ADDR_LS);
335 advk_writel(pcie, 0, PIO_ADDR_MS);
337 /* Start the transfer */
338 advk_writel(pcie, 1, PIO_START);
340 if (!pcie_advk_wait_pio(pcie))
343 /* Check PIO status and get the read result */
344 ret = pcie_advk_check_pio_status(pcie, true, ®);
348 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
350 *valuep = pci_conv_32_to_size(reg, offset, size);
356 * pcie_calc_datastrobe() - Calculate data strobe
358 * @offset: The offset into the device's configuration space
359 * @size: Indicates the size of access to perform
361 * Calculate data strobe according to offset and size
364 static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
366 uint bytes, data_strobe;
379 data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
385 * pcie_advk_write_config() - Write to configuration space
387 * @bus: Pointer to the PCI bus
388 * @bdf: Identifies the PCIe device to access
389 * @offset: The offset into the device's configuration space
390 * @value: The value to write
391 * @size: Indicates the size of access to perform
393 * Write the value @value of size @size from offset @offset within the
394 * configuration space of the device identified by the bus, device & function
395 * numbers in @bdf on the PCI bus @bus.
397 * Return: 0 on success
399 static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
400 uint offset, ulong value,
401 enum pci_size_t size)
403 struct pcie_advk *pcie = dev_get_priv(bus);
406 dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
407 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
408 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
409 offset, size, value);
411 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
412 dev_dbg(pcie->dev, "- out of range\n");
417 advk_writel(pcie, 0, PIO_START);
418 advk_writel(pcie, 1, PIO_ISR);
420 /* Program the control register */
421 reg = advk_readl(pcie, PIO_CTRL);
422 reg &= ~PIO_CTRL_TYPE_MASK;
423 if (PCI_BUS(bdf) == pcie->first_busno)
424 reg |= PCIE_CONFIG_WR_TYPE0;
426 reg |= PCIE_CONFIG_WR_TYPE1;
427 advk_writel(pcie, reg, PIO_CTRL);
429 /* Program the address registers */
430 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
431 advk_writel(pcie, reg, PIO_ADDR_LS);
432 advk_writel(pcie, 0, PIO_ADDR_MS);
433 dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
435 /* Program the data register */
436 reg = pci_conv_size_to_32(0, value, offset, size);
437 advk_writel(pcie, reg, PIO_WR_DATA);
438 dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
440 /* Program the data strobe */
441 reg = pcie_calc_datastrobe(offset, size);
442 advk_writel(pcie, reg, PIO_WR_DATA_STRB);
443 dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
445 /* Start the transfer */
446 advk_writel(pcie, 1, PIO_START);
448 if (!pcie_advk_wait_pio(pcie)) {
449 dev_dbg(pcie->dev, "- wait pio timeout\n");
453 /* Check PIO status */
454 pcie_advk_check_pio_status(pcie, false, ®);
460 * pcie_advk_link_up() - Check if PCIe link is up or not
462 * @pcie: The PCI device to access
464 * Return 1 (true) on link up.
465 * Return 0 (false) on link down.
467 static int pcie_advk_link_up(struct pcie_advk *pcie)
469 u32 val, ltssm_state;
471 val = advk_readl(pcie, CFG_REG);
472 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
473 return ltssm_state >= LTSSM_L0;
477 * pcie_advk_wait_for_link() - Wait for link training to be accomplished
479 * @pcie: The PCI device to access
481 * Wait up to 1 second for link training to be accomplished.
483 * Return 1 (true) if link training ends up with link up success.
484 * Return 0 (false) if link training ends up with link up failure.
486 static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
490 /* check if the link is up or not */
491 for (retries = 0; retries < MAX_RETRIES; retries++) {
492 if (pcie_advk_link_up(pcie)) {
493 printf("PCIE-%d: Link up\n", pcie->first_busno);
497 udelay(LINK_WAIT_TIMEOUT);
500 printf("PCIE-%d: Link down\n", pcie->first_busno);
506 * pcie_advk_setup_hw() - PCIe initailzation
508 * @pcie: The PCI device to access
510 * Return: 0 on success
512 static int pcie_advk_setup_hw(struct pcie_advk *pcie)
516 /* Set to Direct mode */
517 reg = advk_readl(pcie, CTRL_CONFIG_REG);
518 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
519 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
520 advk_writel(pcie, reg, CTRL_CONFIG_REG);
522 /* Set PCI global control register to RC mode */
523 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
524 reg |= (IS_RC_MSK << IS_RC_SHIFT);
525 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
527 /* Set Advanced Error Capabilities and Control PF0 register */
528 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
529 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
530 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
531 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
532 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
534 /* Set PCIe Device Control and Status 1 PF0 register */
535 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
536 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
537 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
539 /* Program PCIe Control 2 to disable strict ordering */
540 reg = PCIE_CORE_CTRL2_RESERVED |
541 PCIE_CORE_CTRL2_TD_ENABLE;
542 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
545 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
546 reg &= ~PCIE_GEN_SEL_MSK;
548 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
551 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
552 reg &= ~LANE_CNT_MSK;
554 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
556 /* Enable link training */
557 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
558 reg |= LINK_TRAINING_EN;
559 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
562 * Enable AXI address window location generation:
563 * When it is enabled, the default outbound window
564 * configurations (Default User Field: 0xD0074CFC)
565 * are used to transparent address translation for
566 * the outbound transactions. Thus, PCIe address
567 * windows are not required.
569 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
570 reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
571 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
574 * Bypass the address window mapping for PIO:
575 * Since PIO access already contains all required
576 * info over AXI interface by PIO registers, the
577 * address window is not required.
579 reg = advk_readl(pcie, PIO_CTRL);
580 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
581 advk_writel(pcie, reg, PIO_CTRL);
583 /* Start link training */
584 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
585 reg |= PCIE_CORE_LINK_TRAINING;
586 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
588 /* Wait for PCIe link up */
589 if (pcie_advk_wait_for_link(pcie))
592 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
593 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
594 PCIE_CORE_CMD_IO_ACCESS_EN |
595 PCIE_CORE_CMD_MEM_IO_REQ_EN;
596 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
602 * pcie_advk_probe() - Probe the PCIe bus for active link
604 * @dev: A pointer to the device being operated on
606 * Probe for an active link on the PCIe bus and configure the controller
607 * to enable this port.
609 * Return: 0 on success, else -ENODEV
611 static int pcie_advk_probe(struct udevice *dev)
613 struct pcie_advk *pcie = dev_get_priv(dev);
615 #ifdef CONFIG_DM_GPIO
616 struct gpio_desc reset_gpio;
618 gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
621 * Issue reset to add-in card through the dedicated GPIO.
622 * Some boards are connecting the card reset pin to common system
623 * reset wire and others are using separate GPIO port.
624 * In the last case we have to release a reset of the addon card
628 * The PCIe RESET signal is not supposed to be released along
629 * with the SOC RESET signal. It should be lowered as early as
630 * possible before PCIe PHY initialization. Moreover, the PCIe
631 * clock should be gated as well.
633 if (dm_gpio_is_valid(&reset_gpio)) {
634 dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
635 dm_gpio_set_value(&reset_gpio, 0);
637 dm_gpio_set_value(&reset_gpio, 1);
640 dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
641 #endif /* CONFIG_DM_GPIO */
643 pcie->first_busno = dev->seq;
644 pcie->dev = pci_get_controller(dev);
646 return pcie_advk_setup_hw(pcie);
650 * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
652 * @dev: A pointer to the device being operated on
654 * Translate relevant data from the device tree pertaining to device @dev into
655 * state that the driver will later make use of. This state is stored in the
656 * device's private data structure.
658 * Return: 0 on success, else -EINVAL
660 static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
662 struct pcie_advk *pcie = dev_get_priv(dev);
664 /* Get the register base address */
665 pcie->base = (void *)dev_read_addr_index(dev, 0);
666 if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
672 static const struct dm_pci_ops pcie_advk_ops = {
673 .read_config = pcie_advk_read_config,
674 .write_config = pcie_advk_write_config,
677 static const struct udevice_id pcie_advk_ids[] = {
678 { .compatible = "marvell,armada-37xx-pcie" },
682 U_BOOT_DRIVER(pcie_advk) = {
685 .of_match = pcie_advk_ids,
686 .ops = &pcie_advk_ops,
687 .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
688 .probe = pcie_advk_probe,
689 .priv_auto_alloc_size = sizeof(struct pcie_advk),