2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 DECLARE_GLOBAL_DATA_PTR;
24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
26 * Initialize controller and call the common driver/pci pci_hose_scan to
27 * scan for bridges and devices.
29 * Hose fields which need to be pre-initialized by board specific code:
38 #include <asm/fsl_pci.h>
40 /* Freescale-specific PCI config registers */
41 #define FSL_PCI_PBFR 0x44
42 #define FSL_PCIE_CAP_ID 0x4c
43 #define FSL_PCIE_CFG_RDY 0x4b0
45 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
46 pci_dev_t dev, int sub_bus);
47 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
48 pci_dev_t dev, int sub_bus);
49 void pciauto_config_init(struct pci_controller *hose);
51 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
52 #define CONFIG_SYS_PCI_MEMORY_BUS 0
55 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
56 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
59 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
60 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
63 int fsl_pci_setup_inbound_windows(struct pci_region *r)
65 struct pci_region *rgn_base = r;
66 u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
68 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
69 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
70 pci_size_t pci_sz = 1ull << __ilog2_u64(sz);
72 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
73 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
74 pci_set_region(r++, bus_start, phys_start, pci_sz,
75 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
82 pci_sz = 1ull << __ilog2_u64(sz);
84 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
85 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
86 pci_set_region(r++, bus_start, phys_start, pci_sz,
87 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
94 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
96 * On 64-bit capable systems, set up a mapping for all of DRAM
97 * in high pci address space.
99 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
100 /* round up to the next largest power of two */
101 if (gd->ram_size > pci_sz)
102 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
103 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
104 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
105 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
108 CONFIG_SYS_PCI64_MEMORY_BUS,
109 CONFIG_SYS_PCI_MEMORY_PHYS,
111 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
112 PCI_REGION_PREFETCH);
114 pci_sz = 1ull << __ilog2_u64(sz);
116 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
117 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
118 pci_set_region(r++, bus_start, phys_start, pci_sz,
119 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
120 PCI_REGION_PREFETCH);
123 phys_start += pci_sz;
127 #ifdef CONFIG_PHYS_64BIT
128 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
129 printf("Was not able to map all of memory via "
130 "inbound windows -- %lld remaining\n", sz);
136 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
140 int busno = hose->first_busno;
147 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
148 pci_dev_t dev = PCI_BDF(busno,0,0);
150 /* Initialize ATMU registers based on hose regions and flags */
151 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
152 volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */
158 pci_setup_indirect(hose, cfg_addr, cfg_data);
160 for (r=0; r<hose->region_count; r++) {
161 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
162 if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */
163 u32 flag = PIWAR_EN | PIWAR_LOCAL |
164 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
165 pi->pitar = (hose->regions[r].phys_start >> 12);
166 pi->piwbar = (hose->regions[r].bus_start >> 12);
167 #ifdef CONFIG_SYS_PCI_64BIT
168 pi->piwbear = (hose->regions[r].bus_start >> 44);
172 if (hose->regions[r].flags & PCI_REGION_PREFETCH)
174 pi->piwar = flag | sz;
176 inbound = hose->regions[r].size > 0;
177 } else { /* Outbound */
178 po->powbar = (hose->regions[r].phys_start >> 12);
179 po->potar = (hose->regions[r].bus_start >> 12);
180 #ifdef CONFIG_SYS_PCI_64BIT
181 po->potear = (hose->regions[r].bus_start >> 44);
185 if (hose->regions[r].flags & PCI_REGION_IO)
186 po->powar = POWAR_EN | sz |
187 POWAR_IO_READ | POWAR_IO_WRITE;
189 po->powar = POWAR_EN | sz |
190 POWAR_MEM_READ | POWAR_MEM_WRITE;
195 pci_register_hose(hose);
196 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
197 hose->current_busno = hose->first_busno;
199 pci->pedr = 0xffffffff; /* Clear any errors */
200 pci->peer = ~0x20140; /* Enable All Error Interupts except
201 * - Master abort (pci)
202 * - Master PERR (pci)
205 pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
206 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
207 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
209 pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8);
210 bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */
214 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
215 enabled = ltssm >= PCI_LTSSM_L0;
217 #ifdef CONFIG_FSL_PCIE_RESET
220 debug("....PCIe link error. "
221 "LTSSM=0x%02x.", ltssm);
222 pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
223 temp32 = pci->pdb_stat;
225 debug(" Asserting PCIe reset @%x = %x\n",
226 &pci->pdb_stat, pci->pdb_stat);
227 pci->pdb_stat &= ~0x08000000; /* clear reset */
229 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
230 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
233 debug("....PCIe link error. "
234 "LTSSM=0x%02x.\n", ltssm);
236 enabled = ltssm >= PCI_LTSSM_L0;
241 debug("....PCIE link error. Skipping scan."
242 "LTSSM=0x%02x\n", ltssm);
243 hose->last_busno = hose->first_busno;
247 pci->pme_msg_det = 0xffffffff;
248 pci->pme_msg_int_en = 0xffffffff;
250 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
251 neg_link_w = (temp16 & 0x3f0 ) >> 4;
252 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
255 hose->current_busno++; /* Start scan with secondary */
256 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
260 /* Use generic setup_device to initialize standard pci regs,
261 * but do not allocate any windows since any BAR found (such
262 * as PCSRBAR) is not in this cpu's memory space.
265 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
266 hose->pci_prefetch, hose->pci_io);
269 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
270 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
271 temp16 | PCI_COMMAND_MEMORY);
274 #ifndef CONFIG_PCI_NOSCAN
275 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
277 /* Programming Interface (PCI_CLASS_PROG)
278 * 0 == pci host or pcie root-complex,
279 * 1 == pci agent or pcie end-point
282 printf(" Scanning PCI bus %02x\n",
283 hose->current_busno);
284 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
286 debug(" Not scanning PCI bus %02x. PI=%x\n",
287 hose->current_busno, temp8);
288 hose->last_busno = hose->current_busno;
291 if ( bridge ) { /* update limit regs and subordinate busno */
292 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
295 hose->last_busno = hose->current_busno;
298 /* Clear all error indications */
301 pci->pme_msg_det = 0xffffffff;
302 pci->pedr = 0xffffffff;
304 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
306 pci_hose_write_config_word(hose, dev,
310 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
312 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
316 /* Enable inbound PCI config cycles for agent/endpoint interface */
317 void fsl_pci_config_unlock(struct pci_controller *hose)
319 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
324 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
328 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
329 if (pcie_cap != 0x0) {
330 /* PCIe - set CFG_READY bit of Configuration Ready Register */
331 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
333 /* PCI - clear ACL bit of PBFR */
334 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
336 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
340 #ifdef CONFIG_OF_BOARD_SETUP
342 #include <fdt_support.h>
344 void ft_fsl_pci_setup(void *blob, const char *pci_alias,
345 struct pci_controller *hose)
347 int off = fdt_path_offset(blob, pci_alias);
353 bus_range[1] = hose->last_busno - hose->first_busno;
354 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
355 fdt_pci_dma_ranges(blob, off, hose);