2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
24 * Initialize controller and call the common driver/pci pci_hose_scan to
25 * scan for bridges and devices.
27 * Hose fields which need to be pre-initialized by board specific code:
36 #include <asm/immap_fsl_pci.h>
38 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
39 pci_dev_t dev, int sub_bus);
40 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
41 pci_dev_t dev, int sub_bus);
42 void pciauto_config_init(struct pci_controller *hose);
44 void fsl_pci_init(struct pci_controller *hose)
48 int busno = hose->first_busno;
55 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
56 pci_dev_t dev = PCI_BDF(busno,0,0);
58 /* Initialize ATMU registers based on hose regions and flags */
59 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
60 volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */
66 for (r=0; r<hose->region_count; r++) {
67 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
68 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
69 u32 flag = PIWAR_EN | PIWAR_LOCAL | \
70 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
71 pi->pitar = (hose->regions[r].phys_start >> 12);
72 pi->piwbar = (hose->regions[r].bus_start >> 12);
73 #ifdef CONFIG_SYS_PCI_64BIT
74 pi->piwbear = (hose->regions[r].bus_start >> 44);
78 if (hose->regions[r].flags & PCI_REGION_PREFETCH)
80 pi->piwar = flag | sz;
82 inbound = hose->regions[r].size > 0;
83 } else { /* Outbound */
84 po->powbar = (hose->regions[r].phys_start >> 12);
85 po->potar = (hose->regions[r].bus_start >> 12);
86 #ifdef CONFIG_SYS_PCI_64BIT
87 po->potear = (hose->regions[r].bus_start >> 44);
91 if (hose->regions[r].flags & PCI_REGION_IO)
92 po->powar = POWAR_EN | sz | \
93 POWAR_IO_READ | POWAR_IO_WRITE;
95 po->powar = POWAR_EN | sz | \
96 POWAR_MEM_READ | POWAR_MEM_WRITE;
101 pci_register_hose(hose);
102 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
103 hose->current_busno = hose->first_busno;
105 pci->pedr = 0xffffffff; /* Clear any errors */
106 pci->peer = ~0x20140; /* Enable All Error Interupts except
107 * - Master abort (pci)
108 * - Master PERR (pci)
111 pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
112 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
113 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
115 pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8);
116 bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */
120 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
121 enabled = ltssm >= PCI_LTSSM_L0;
123 #ifdef CONFIG_FSL_PCIE_RESET
126 debug("....PCIe link error. "
127 "LTSSM=0x%02x.", ltssm);
128 pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
129 temp32 = pci->pdb_stat;
131 debug(" Asserting PCIe reset @%x = %x\n",
132 &pci->pdb_stat, pci->pdb_stat);
133 pci->pdb_stat &= ~0x08000000; /* clear reset */
135 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
136 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
139 debug("....PCIe link error. "
140 "LTSSM=0x%02x.\n", ltssm);
142 enabled = ltssm >= PCI_LTSSM_L0;
147 debug("....PCIE link error. Skipping scan."
148 "LTSSM=0x%02x\n", ltssm);
149 hose->last_busno = hose->first_busno;
153 pci->pme_msg_det = 0xffffffff;
154 pci->pme_msg_int_en = 0xffffffff;
156 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
157 neg_link_w = (temp16 & 0x3f0 ) >> 4;
158 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
161 hose->current_busno++; /* Start scan with secondary */
162 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
166 /* Use generic setup_device to initialize standard pci regs,
167 * but do not allocate any windows since any BAR found (such
168 * as PCSRBAR) is not in this cpu's memory space.
171 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
172 hose->pci_prefetch, hose->pci_io);
175 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
176 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
177 temp16 | PCI_COMMAND_MEMORY);
180 #ifndef CONFIG_PCI_NOSCAN
181 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
183 /* Programming Interface (PCI_CLASS_PROG)
184 * 0 == pci host or pcie root-complex,
185 * 1 == pci agent or pcie end-point
188 printf(" Scanning PCI bus %02x\n",
189 hose->current_busno);
190 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
192 debug(" Not scanning PCI bus %02x. PI=%x\n",
193 hose->current_busno, temp8);
194 hose->last_busno = hose->current_busno;
197 if ( bridge ) { /* update limit regs and subordinate busno */
198 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
201 hose->last_busno = hose->current_busno;
204 /* Clear all error indications */
207 pci->pme_msg_det = 0xffffffff;
208 pci->pedr = 0xffffffff;
210 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
212 pci_hose_write_config_word(hose, dev,
216 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
218 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);