5 Enable support for PCI (Peripheral Interconnect Bus), a type of bus
6 used on some devices to allow the CPU to communicate with its
12 bool "Enable driver model for PCI"
15 Use driver model for PCI. Driver model is the new method for
16 orgnising devices in U-Boot. For PCI, driver model keeps track of
17 available PCI devices, allows scanning of PCI buses and provides
18 device configuration support.
21 bool "Enable compatible functions for PCI"
24 Enable compatibility functions for PCI so that old code can be used
25 with CONFIG_DM_PCI enabled. This should be used as an interim
26 measure when porting a board to use driver model for PCI. Once the
27 board is fully supported, this option should be disabled.
30 bool "Enable Plug & Play support for PCI"
31 depends on PCI || DM_PCI
34 Enable PCI memory and I/O space resource allocation and assignment.
36 config PCIE_ECAM_GENERIC
37 bool "Generic ECAM-based PCI host controller support"
41 Say Y here if you want to enable support for generic ECAM-based
42 PCIe host controllers, such as the one emulated by QEMU.
45 bool "Enable Armada-8K PCIe driver (DesignWare core)"
49 Say Y here if you want to enable PCIe controller support on
50 Armada-8K SoCs. The PCIe controller on Armada-8K is based on
54 bool "Renesas RCar Gen2 PCIe driver"
58 Say Y here if you want to enable PCIe controller support on
59 Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is
60 also used to access EHCI USB controller on the SoC.
63 bool "Sandbox PCI support"
64 depends on SANDBOX && DM_PCI
66 Support PCI on sandbox, as an emulated bus. This permits testing of
67 PCI feature such as bus scanning, device configuration and device
68 access. The available (emulated) devices are defined statically in
69 the device tree but the normal PCI scan technique is used to find
73 bool "Tegra PCI support"
75 depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
77 Enable support for the PCIe controller found on some generations of
78 Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
79 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
80 with a total of 5 lanes. Some boards require this for Ethernet
81 support to work (e.g. beaver, jetson-tk1).
84 bool "Xilinx AXI Bridge for PCI Express"
87 Enable support for the Xilinx AXI bridge for PCI express, an IP block
88 which can be used on some generations of Xilinx FPGAs.
90 config PCIE_LAYERSCAPE
91 bool "Layerscape PCIe support"
94 Support Layerscape PCIe. The Layerscape SoC may have one or several
95 PCIe controllers. The PCIe may works in RC or EP mode according to
96 RCW[HOST_AGT_PEX] setting.