5 Enable support for PCI (Peripheral Interconnect Bus), a type of bus
6 used on some devices to allow the CPU to communicate with its
12 bool "Enable driver model for PCI"
15 Use driver model for PCI. Driver model is the new method for
16 orgnising devices in U-Boot. For PCI, driver model keeps track of
17 available PCI devices, allows scanning of PCI buses and provides
18 device configuration support.
21 bool "Enable compatible functions for PCI"
24 Enable compatibility functions for PCI so that old code can be used
25 with CONFIG_DM_PCI enabled. This should be used as an interim
26 measure when porting a board to use driver model for PCI. Once the
27 board is fully supported, this option should be disabled.
30 bool "Enable Plug & Play support for PCI"
31 depends on PCI || DM_PCI
34 Enable PCI memory and I/O space resource allocation and assignment.
37 bool "Enable Armada-8K PCIe driver (DesignWare core)"
41 Say Y here if you want to enable PCIe controller support on
42 Armada-8K SoCs. The PCIe controller on Armada-8K is based on
46 bool "Sandbox PCI support"
47 depends on SANDBOX && DM_PCI
49 Support PCI on sandbox, as an emulated bus. This permits testing of
50 PCI feature such as bus scanning, device configuration and device
51 access. The available (emulated) devices are defined statically in
52 the device tree but the normal PCI scan technique is used to find
56 bool "Tegra PCI support"
58 depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
60 Enable support for the PCIe controller found on some generations of
61 Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
62 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
63 with a total of 5 lanes. Some boards require this for Ethernet
64 support to work (e.g. beaver, jetson-tk1).
67 bool "Xilinx AXI Bridge for PCI Express"
70 Enable support for the Xilinx AXI bridge for PCI express, an IP block
71 which can be used on some generations of Xilinx FPGAs.
73 config PCIE_LAYERSCAPE
74 bool "Layerscape PCIe support"
77 Support Layerscape PCIe. The Layerscape SoC may have one or several
78 PCIe controllers. The PCIe may works in RC or EP mode according to
79 RCW[HOST_AGT_PEX] setting.