2 * Copyright (C) 2014 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
11 #define BIOS_CTRL 0xd8
13 static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
17 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
18 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
19 rcba = rcba & 0xffffc000;
20 *sbasep = rcba + 0x3020;
25 static int pch7_set_spi_protect(struct udevice *dev, bool protect)
29 /* Adjust the BIOS write protect to dis/allow write commands */
30 dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
32 bios_cntl &= ~BIOS_CTRL_BIOSWE;
34 bios_cntl |= BIOS_CTRL_BIOSWE;
35 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
40 static const struct pch_ops pch7_ops = {
41 .get_spi_base = pch7_get_spi_base,
42 .set_spi_protect = pch7_set_spi_protect,
45 static const struct udevice_id pch7_ids[] = {
46 { .compatible = "intel,pch7" },
50 U_BOOT_DRIVER(pch7_drv) = {