2 * Copyright (C) 2017 NXP Semiconductors
3 * Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __DRIVER_NVME_H__
9 #define __DRIVER_NVME_H__
13 struct nvme_id_power_state {
14 __le16 max_power; /* centiwatts */
17 __le32 entry_lat; /* microseconds */
18 __le32 exit_lat; /* microseconds */
27 __u8 active_work_scale;
32 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
33 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
77 struct nvme_id_power_state psd[32];
82 NVME_CTRL_ONCS_COMPARE = 1 << 0,
83 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
84 NVME_CTRL_ONCS_DSM = 1 << 2,
85 NVME_CTRL_VWC_PRESENT = 1 << 0,
119 struct nvme_lbaf lbaf[16];
125 NVME_NS_FEAT_THIN = 1 << 0,
126 NVME_NS_FLBAS_LBA_MASK = 0xf,
127 NVME_NS_FLBAS_META_EXT = 0x10,
128 NVME_LBAF_RP_BEST = 0,
129 NVME_LBAF_RP_BETTER = 1,
130 NVME_LBAF_RP_GOOD = 2,
131 NVME_LBAF_RP_DEGRADED = 3,
132 NVME_NS_DPC_PI_LAST = 1 << 4,
133 NVME_NS_DPC_PI_FIRST = 1 << 3,
134 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
135 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
136 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
137 NVME_NS_DPS_PI_FIRST = 1 << 3,
138 NVME_NS_DPS_PI_MASK = 0x7,
139 NVME_NS_DPS_PI_TYPE1 = 1,
140 NVME_NS_DPS_PI_TYPE2 = 2,
141 NVME_NS_DPS_PI_TYPE3 = 3,
144 struct nvme_smart_log {
145 __u8 critical_warning;
151 __u8 data_units_read[16];
152 __u8 data_units_written[16];
154 __u8 host_writes[16];
155 __u8 ctrl_busy_time[16];
156 __u8 power_cycles[16];
157 __u8 power_on_hours[16];
158 __u8 unsafe_shutdowns[16];
159 __u8 media_errors[16];
160 __u8 num_err_log_entries[16];
161 __le32 warning_temp_time;
162 __le32 critical_comp_time;
163 __le16 temp_sensor[8];
168 NVME_SMART_CRIT_SPARE = 1 << 0,
169 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
170 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
171 NVME_SMART_CRIT_MEDIA = 1 << 3,
172 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
175 struct nvme_lba_range_type {
186 NVME_LBART_TYPE_FS = 0x01,
187 NVME_LBART_TYPE_RAID = 0x02,
188 NVME_LBART_TYPE_CACHE = 0x03,
189 NVME_LBART_TYPE_SWAP = 0x04,
191 NVME_LBART_ATTRIB_TEMP = 1 << 0,
192 NVME_LBART_ATTRIB_HIDE = 1 << 1,
195 struct nvme_reservation_status {
214 nvme_cmd_flush = 0x00,
215 nvme_cmd_write = 0x01,
216 nvme_cmd_read = 0x02,
217 nvme_cmd_write_uncor = 0x04,
218 nvme_cmd_compare = 0x05,
219 nvme_cmd_write_zeroes = 0x08,
221 nvme_cmd_resv_register = 0x0d,
222 nvme_cmd_resv_report = 0x0e,
223 nvme_cmd_resv_acquire = 0x11,
224 nvme_cmd_resv_release = 0x15,
227 struct nvme_common_command {
239 struct nvme_rw_command {
258 NVME_RW_LR = 1 << 15,
259 NVME_RW_FUA = 1 << 14,
260 NVME_RW_DSM_FREQ_UNSPEC = 0,
261 NVME_RW_DSM_FREQ_TYPICAL = 1,
262 NVME_RW_DSM_FREQ_RARE = 2,
263 NVME_RW_DSM_FREQ_READS = 3,
264 NVME_RW_DSM_FREQ_WRITES = 4,
265 NVME_RW_DSM_FREQ_RW = 5,
266 NVME_RW_DSM_FREQ_ONCE = 6,
267 NVME_RW_DSM_FREQ_PREFETCH = 7,
268 NVME_RW_DSM_FREQ_TEMP = 8,
269 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
270 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
271 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
272 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
273 NVME_RW_DSM_SEQ_REQ = 1 << 6,
274 NVME_RW_DSM_COMPRESSED = 1 << 7,
275 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
276 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
277 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
278 NVME_RW_PRINFO_PRACT = 1 << 13,
281 struct nvme_dsm_cmd {
295 NVME_DSMGMT_IDR = 1 << 0,
296 NVME_DSMGMT_IDW = 1 << 1,
297 NVME_DSMGMT_AD = 1 << 2,
300 struct nvme_dsm_range {
308 enum nvme_admin_opcode {
309 nvme_admin_delete_sq = 0x00,
310 nvme_admin_create_sq = 0x01,
311 nvme_admin_get_log_page = 0x02,
312 nvme_admin_delete_cq = 0x04,
313 nvme_admin_create_cq = 0x05,
314 nvme_admin_identify = 0x06,
315 nvme_admin_abort_cmd = 0x08,
316 nvme_admin_set_features = 0x09,
317 nvme_admin_get_features = 0x0a,
318 nvme_admin_async_event = 0x0c,
319 nvme_admin_activate_fw = 0x10,
320 nvme_admin_download_fw = 0x11,
321 nvme_admin_format_nvm = 0x80,
322 nvme_admin_security_send = 0x81,
323 nvme_admin_security_recv = 0x82,
327 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
328 NVME_CQ_IRQ_ENABLED = (1 << 1),
329 NVME_SQ_PRIO_URGENT = (0 << 1),
330 NVME_SQ_PRIO_HIGH = (1 << 1),
331 NVME_SQ_PRIO_MEDIUM = (2 << 1),
332 NVME_SQ_PRIO_LOW = (3 << 1),
333 NVME_FEAT_ARBITRATION = 0x01,
334 NVME_FEAT_POWER_MGMT = 0x02,
335 NVME_FEAT_LBA_RANGE = 0x03,
336 NVME_FEAT_TEMP_THRESH = 0x04,
337 NVME_FEAT_ERR_RECOVERY = 0x05,
338 NVME_FEAT_VOLATILE_WC = 0x06,
339 NVME_FEAT_NUM_QUEUES = 0x07,
340 NVME_FEAT_IRQ_COALESCE = 0x08,
341 NVME_FEAT_IRQ_CONFIG = 0x09,
342 NVME_FEAT_WRITE_ATOMIC = 0x0a,
343 NVME_FEAT_ASYNC_EVENT = 0x0b,
344 NVME_FEAT_AUTO_PST = 0x0c,
345 NVME_FEAT_SW_PROGRESS = 0x80,
346 NVME_FEAT_HOST_ID = 0x81,
347 NVME_FEAT_RESV_MASK = 0x82,
348 NVME_FEAT_RESV_PERSIST = 0x83,
349 NVME_LOG_ERROR = 0x01,
350 NVME_LOG_SMART = 0x02,
351 NVME_LOG_FW_SLOT = 0x03,
352 NVME_LOG_RESERVATION = 0x80,
353 NVME_FWACT_REPL = (0 << 3),
354 NVME_FWACT_REPL_ACTV = (1 << 3),
355 NVME_FWACT_ACTV = (2 << 3),
358 struct nvme_identify {
370 struct nvme_features {
383 struct nvme_create_cq {
397 struct nvme_create_sq {
411 struct nvme_delete_queue {
421 struct nvme_abort_cmd {
431 struct nvme_download_firmware {
443 struct nvme_format_cmd {
453 struct nvme_command {
455 struct nvme_common_command common;
456 struct nvme_rw_command rw;
457 struct nvme_identify identify;
458 struct nvme_features features;
459 struct nvme_create_cq create_cq;
460 struct nvme_create_sq create_sq;
461 struct nvme_delete_queue delete_queue;
462 struct nvme_download_firmware dlfw;
463 struct nvme_format_cmd format;
464 struct nvme_dsm_cmd dsm;
465 struct nvme_abort_cmd abort;
470 NVME_SC_SUCCESS = 0x0,
471 NVME_SC_INVALID_OPCODE = 0x1,
472 NVME_SC_INVALID_FIELD = 0x2,
473 NVME_SC_CMDID_CONFLICT = 0x3,
474 NVME_SC_DATA_XFER_ERROR = 0x4,
475 NVME_SC_POWER_LOSS = 0x5,
476 NVME_SC_INTERNAL = 0x6,
477 NVME_SC_ABORT_REQ = 0x7,
478 NVME_SC_ABORT_QUEUE = 0x8,
479 NVME_SC_FUSED_FAIL = 0x9,
480 NVME_SC_FUSED_MISSING = 0xa,
481 NVME_SC_INVALID_NS = 0xb,
482 NVME_SC_CMD_SEQ_ERROR = 0xc,
483 NVME_SC_SGL_INVALID_LAST = 0xd,
484 NVME_SC_SGL_INVALID_COUNT = 0xe,
485 NVME_SC_SGL_INVALID_DATA = 0xf,
486 NVME_SC_SGL_INVALID_METADATA = 0x10,
487 NVME_SC_SGL_INVALID_TYPE = 0x11,
488 NVME_SC_LBA_RANGE = 0x80,
489 NVME_SC_CAP_EXCEEDED = 0x81,
490 NVME_SC_NS_NOT_READY = 0x82,
491 NVME_SC_RESERVATION_CONFLICT = 0x83,
492 NVME_SC_CQ_INVALID = 0x100,
493 NVME_SC_QID_INVALID = 0x101,
494 NVME_SC_QUEUE_SIZE = 0x102,
495 NVME_SC_ABORT_LIMIT = 0x103,
496 NVME_SC_ABORT_MISSING = 0x104,
497 NVME_SC_ASYNC_LIMIT = 0x105,
498 NVME_SC_FIRMWARE_SLOT = 0x106,
499 NVME_SC_FIRMWARE_IMAGE = 0x107,
500 NVME_SC_INVALID_VECTOR = 0x108,
501 NVME_SC_INVALID_LOG_PAGE = 0x109,
502 NVME_SC_INVALID_FORMAT = 0x10a,
503 NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b,
504 NVME_SC_INVALID_QUEUE = 0x10c,
505 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
506 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
507 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
508 NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110,
509 NVME_SC_BAD_ATTRIBUTES = 0x180,
510 NVME_SC_INVALID_PI = 0x181,
511 NVME_SC_READ_ONLY = 0x182,
512 NVME_SC_WRITE_FAULT = 0x280,
513 NVME_SC_READ_ERROR = 0x281,
514 NVME_SC_GUARD_CHECK = 0x282,
515 NVME_SC_APPTAG_CHECK = 0x283,
516 NVME_SC_REFTAG_CHECK = 0x284,
517 NVME_SC_COMPARE_FAILED = 0x285,
518 NVME_SC_ACCESS_DENIED = 0x286,
519 NVME_SC_DNR = 0x4000,
522 struct nvme_completion {
523 __le32 result; /* Used by admin commands to return data */
525 __le16 sq_head; /* how much of this queue may be reclaimed */
526 __le16 sq_id; /* submission queue that generated this entry */
527 __u16 command_id; /* of the command which completed */
528 __le16 status; /* did the command fail, and if so, why? */
532 * Registers should always be accessed with double word or quad word
533 * accesses. Registers with 64-bit address pointers should be written
534 * to with dword accesses by writing the low dword first (ptr[0]),
535 * then the high dword (ptr[1]) second.
537 static inline u64 nvme_readq(__le64 volatile *regs)
539 #if BITS_PER_LONG == 64
542 __u32 *ptr = (__u32 *)regs;
543 u64 val_lo = readl(ptr);
544 u64 val_hi = readl(ptr + 1);
546 return val_lo + (val_hi << 32);
550 static inline void nvme_writeq(const u64 val, __le64 volatile *regs)
552 #if BITS_PER_LONG == 64
555 __u32 *ptr = (__u32 *)regs;
556 u32 val_lo = lower_32_bits(val);
557 u32 val_hi = upper_32_bits(val);
559 writel(val_hi, ptr + 1);
564 __u64 cap; /* Controller Capabilities */
565 __u32 vs; /* Version */
566 __u32 intms; /* Interrupt Mask Set */
567 __u32 intmc; /* Interrupt Mask Clear */
568 __u32 cc; /* Controller Configuration */
569 __u32 rsvd1; /* Reserved */
570 __u32 csts; /* Controller Status */
571 __u32 rsvd2; /* Reserved */
572 __u32 aqa; /* Admin Queue Attributes */
573 __u64 asq; /* Admin SQ Base Address */
574 __u64 acq; /* Admin CQ Base Address */
577 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
578 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
579 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
580 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
581 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
583 #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
586 NVME_CC_ENABLE = 1 << 0,
587 NVME_CC_CSS_NVM = 0 << 4,
588 NVME_CC_MPS_SHIFT = 7,
589 NVME_CC_ARB_RR = 0 << 11,
590 NVME_CC_ARB_WRRU = 1 << 11,
591 NVME_CC_ARB_VS = 7 << 11,
592 NVME_CC_SHN_NONE = 0 << 14,
593 NVME_CC_SHN_NORMAL = 1 << 14,
594 NVME_CC_SHN_ABRUPT = 2 << 14,
595 NVME_CC_SHN_MASK = 3 << 14,
596 NVME_CC_IOSQES = 6 << 16,
597 NVME_CC_IOCQES = 4 << 20,
598 NVME_CSTS_RDY = 1 << 0,
599 NVME_CSTS_CFS = 1 << 1,
600 NVME_CSTS_SHST_NORMAL = 0 << 2,
601 NVME_CSTS_SHST_OCCUR = 1 << 2,
602 NVME_CSTS_SHST_CMPLT = 2 << 2,
603 NVME_CSTS_SHST_MASK = 3 << 2,
606 /* Represents an NVM Express device. Each nvme_dev is a PCI function. */
608 struct list_head node;
609 struct nvme_queue **queues;
612 unsigned queue_count;
613 unsigned online_queues;
618 struct nvme_bar __iomem *bar;
619 struct list_head namespaces;
622 char firmware_rev[8];
623 u32 max_transfer_shift;
634 * An NVM Express namespace is equivalent to a SCSI LUN.
635 * Each namespace is operated as an independent "device".
638 struct list_head list;
639 struct nvme_dev *dev;
644 u64 mode_select_num_blocks;
645 u32 mode_select_block_len;
648 #endif /* __DRIVER_NVME_H__ */