1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 NXP Semiconductors
4 * Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com>
14 #include <dm/device-internal.h>
17 #define NVME_Q_DEPTH 2
18 #define NVME_AQ_DEPTH 2
19 #define NVME_SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
20 #define NVME_CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
21 #define ADMIN_TIMEOUT 60
23 #define MAX_PRP_POOL 512
32 * An NVM Express queue. Each device has at least two (one for admin
33 * commands and one for I/O commands).
37 struct nvme_command *sq_cmds;
38 struct nvme_completion *cqes;
39 wait_queue_head_t sq_full;
49 unsigned long cmdid_data[];
52 static int nvme_wait_ready(struct nvme_dev *dev, bool enabled)
54 u32 bit = enabled ? NVME_CSTS_RDY : 0;
58 /* Timeout field in the CAP register is in 500 millisecond units */
59 timeout = NVME_CAP_TIMEOUT(dev->cap) * 500;
62 while (get_timer(start) < timeout) {
63 if ((readl(&dev->bar->csts) & NVME_CSTS_RDY) == bit)
70 static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
71 int total_len, u64 dma_addr)
73 u32 page_size = dev->page_size;
74 int offset = dma_addr & (page_size - 1);
76 int length = total_len;
78 u32 prps_per_page = (page_size >> 3) - 1;
81 length -= (page_size - offset);
89 dma_addr += (page_size - offset);
91 if (length <= page_size) {
96 nprps = DIV_ROUND_UP(length, page_size);
97 num_pages = DIV_ROUND_UP(nprps, prps_per_page);
99 if (nprps > dev->prp_entry_num) {
102 * Always increase in increments of pages. It doesn't waste
103 * much memory and reduces the number of allocations.
105 dev->prp_pool = memalign(page_size, num_pages * page_size);
106 if (!dev->prp_pool) {
107 printf("Error: malloc prp_pool fail\n");
110 dev->prp_entry_num = prps_per_page * num_pages;
113 prp_pool = dev->prp_pool;
116 if (i == ((page_size >> 3) - 1)) {
117 *(prp_pool + i) = cpu_to_le64((ulong)prp_pool +
120 prp_pool += page_size;
122 *(prp_pool + i++) = cpu_to_le64(dma_addr);
123 dma_addr += page_size;
126 *prp2 = (ulong)dev->prp_pool;
128 flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool +
129 dev->prp_entry_num * sizeof(u64));
134 static __le16 nvme_get_cmd_id(void)
136 static unsigned short cmdid;
138 return cpu_to_le16((cmdid < USHRT_MAX) ? cmdid++ : 0);
141 static u16 nvme_read_completion_status(struct nvme_queue *nvmeq, u16 index)
143 u64 start = (ulong)&nvmeq->cqes[index];
144 u64 stop = start + sizeof(struct nvme_completion);
146 invalidate_dcache_range(start, stop);
148 return le16_to_cpu(readw(&(nvmeq->cqes[index].status)));
152 * nvme_submit_cmd() - copy a command into a queue and ring the doorbell
154 * @nvmeq: The queue to use
155 * @cmd: The command to send
157 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
159 u16 tail = nvmeq->sq_tail;
161 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
162 flush_dcache_range((ulong)&nvmeq->sq_cmds[tail],
163 (ulong)&nvmeq->sq_cmds[tail] + sizeof(*cmd));
165 if (++tail == nvmeq->q_depth)
167 writel(tail, nvmeq->q_db);
168 nvmeq->sq_tail = tail;
171 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
172 struct nvme_command *cmd,
173 u32 *result, unsigned timeout)
175 u16 head = nvmeq->cq_head;
176 u16 phase = nvmeq->cq_phase;
179 ulong timeout_us = timeout * 100000;
181 cmd->common.command_id = nvme_get_cmd_id();
182 nvme_submit_cmd(nvmeq, cmd);
184 start_time = timer_get_us();
187 status = nvme_read_completion_status(nvmeq, head);
188 if ((status & 0x01) == phase)
190 if (timeout_us > 0 && (timer_get_us() - start_time)
197 printf("ERROR: status = %x, phase = %d, head = %d\n",
198 status, phase, head);
200 if (++head == nvmeq->q_depth) {
204 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
205 nvmeq->cq_head = head;
206 nvmeq->cq_phase = phase;
212 *result = le32_to_cpu(readl(&(nvmeq->cqes[head].result)));
214 if (++head == nvmeq->q_depth) {
218 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
219 nvmeq->cq_head = head;
220 nvmeq->cq_phase = phase;
225 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
228 return nvme_submit_sync_cmd(dev->queues[NVME_ADMIN_Q], cmd,
229 result, ADMIN_TIMEOUT);
232 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev,
235 struct nvme_queue *nvmeq = malloc(sizeof(*nvmeq));
238 memset(nvmeq, 0, sizeof(*nvmeq));
240 nvmeq->cqes = (void *)memalign(4096, NVME_CQ_SIZE(depth));
243 memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(depth));
245 nvmeq->sq_cmds = (void *)memalign(4096, NVME_SQ_SIZE(depth));
248 memset((void *)nvmeq->sq_cmds, 0, NVME_SQ_SIZE(depth));
254 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
255 nvmeq->q_depth = depth;
258 dev->queues[qid] = nvmeq;
263 free((void *)nvmeq->cqes);
270 static int nvme_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
272 struct nvme_command c;
274 memset(&c, 0, sizeof(c));
275 c.delete_queue.opcode = opcode;
276 c.delete_queue.qid = cpu_to_le16(id);
278 return nvme_submit_admin_cmd(dev, &c, NULL);
281 static int nvme_delete_sq(struct nvme_dev *dev, u16 sqid)
283 return nvme_delete_queue(dev, nvme_admin_delete_sq, sqid);
286 static int nvme_delete_cq(struct nvme_dev *dev, u16 cqid)
288 return nvme_delete_queue(dev, nvme_admin_delete_cq, cqid);
291 static int nvme_enable_ctrl(struct nvme_dev *dev)
293 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
294 dev->ctrl_config |= NVME_CC_ENABLE;
295 writel(cpu_to_le32(dev->ctrl_config), &dev->bar->cc);
297 return nvme_wait_ready(dev, true);
300 static int nvme_disable_ctrl(struct nvme_dev *dev)
302 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
303 dev->ctrl_config &= ~NVME_CC_ENABLE;
304 writel(cpu_to_le32(dev->ctrl_config), &dev->bar->cc);
306 return nvme_wait_ready(dev, false);
309 static void nvme_free_queue(struct nvme_queue *nvmeq)
311 free((void *)nvmeq->cqes);
312 free(nvmeq->sq_cmds);
316 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
320 for (i = dev->queue_count - 1; i >= lowest; i--) {
321 struct nvme_queue *nvmeq = dev->queues[i];
323 dev->queues[i] = NULL;
324 nvme_free_queue(nvmeq);
328 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
330 struct nvme_dev *dev = nvmeq->dev;
335 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
336 memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(nvmeq->q_depth));
337 flush_dcache_range((ulong)nvmeq->cqes,
338 (ulong)nvmeq->cqes + NVME_CQ_SIZE(nvmeq->q_depth));
339 dev->online_queues++;
342 static int nvme_configure_admin_queue(struct nvme_dev *dev)
347 struct nvme_queue *nvmeq;
348 /* most architectures use 4KB as the page size */
349 unsigned page_shift = 12;
350 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
351 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
353 if (page_shift < dev_page_min) {
354 debug("Device minimum page size (%u) too large for host (%u)\n",
355 1 << dev_page_min, 1 << page_shift);
359 if (page_shift > dev_page_max) {
360 debug("Device maximum page size (%u) smaller than host (%u)\n",
361 1 << dev_page_max, 1 << page_shift);
362 page_shift = dev_page_max;
365 result = nvme_disable_ctrl(dev);
369 nvmeq = dev->queues[NVME_ADMIN_Q];
371 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
376 aqa = nvmeq->q_depth - 1;
380 dev->page_size = 1 << page_shift;
382 dev->ctrl_config = NVME_CC_CSS_NVM;
383 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
384 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
385 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
387 writel(aqa, &dev->bar->aqa);
388 nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq);
389 nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq);
391 result = nvme_enable_ctrl(dev);
395 nvmeq->cq_vector = 0;
397 nvme_init_queue(dev->queues[NVME_ADMIN_Q], 0);
402 nvme_free_queues(dev, 0);
407 static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid,
408 struct nvme_queue *nvmeq)
410 struct nvme_command c;
411 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
413 memset(&c, 0, sizeof(c));
414 c.create_cq.opcode = nvme_admin_create_cq;
415 c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes);
416 c.create_cq.cqid = cpu_to_le16(qid);
417 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
418 c.create_cq.cq_flags = cpu_to_le16(flags);
419 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
421 return nvme_submit_admin_cmd(dev, &c, NULL);
424 static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid,
425 struct nvme_queue *nvmeq)
427 struct nvme_command c;
428 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
430 memset(&c, 0, sizeof(c));
431 c.create_sq.opcode = nvme_admin_create_sq;
432 c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds);
433 c.create_sq.sqid = cpu_to_le16(qid);
434 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
435 c.create_sq.sq_flags = cpu_to_le16(flags);
436 c.create_sq.cqid = cpu_to_le16(qid);
438 return nvme_submit_admin_cmd(dev, &c, NULL);
441 int nvme_identify(struct nvme_dev *dev, unsigned nsid,
442 unsigned cns, dma_addr_t dma_addr)
444 struct nvme_command c;
445 u32 page_size = dev->page_size;
446 int offset = dma_addr & (page_size - 1);
447 int length = sizeof(struct nvme_id_ctrl);
450 memset(&c, 0, sizeof(c));
451 c.identify.opcode = nvme_admin_identify;
452 c.identify.nsid = cpu_to_le32(nsid);
453 c.identify.prp1 = cpu_to_le64(dma_addr);
455 length -= (page_size - offset);
459 dma_addr += (page_size - offset);
460 c.identify.prp2 = cpu_to_le64(dma_addr);
463 c.identify.cns = cpu_to_le32(cns);
465 ret = nvme_submit_admin_cmd(dev, &c, NULL);
467 invalidate_dcache_range(dma_addr,
468 dma_addr + sizeof(struct nvme_id_ctrl));
473 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
474 dma_addr_t dma_addr, u32 *result)
476 struct nvme_command c;
478 memset(&c, 0, sizeof(c));
479 c.features.opcode = nvme_admin_get_features;
480 c.features.nsid = cpu_to_le32(nsid);
481 c.features.prp1 = cpu_to_le64(dma_addr);
482 c.features.fid = cpu_to_le32(fid);
485 * TODO: add cache invalidate operation when the size of
486 * the DMA buffer is known
489 return nvme_submit_admin_cmd(dev, &c, result);
492 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
493 dma_addr_t dma_addr, u32 *result)
495 struct nvme_command c;
497 memset(&c, 0, sizeof(c));
498 c.features.opcode = nvme_admin_set_features;
499 c.features.prp1 = cpu_to_le64(dma_addr);
500 c.features.fid = cpu_to_le32(fid);
501 c.features.dword11 = cpu_to_le32(dword11);
504 * TODO: add cache flush operation when the size of
505 * the DMA buffer is known
508 return nvme_submit_admin_cmd(dev, &c, result);
511 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
513 struct nvme_dev *dev = nvmeq->dev;
516 nvmeq->cq_vector = qid - 1;
517 result = nvme_alloc_cq(dev, qid, nvmeq);
521 result = nvme_alloc_sq(dev, qid, nvmeq);
525 nvme_init_queue(nvmeq, qid);
530 nvme_delete_sq(dev, qid);
532 nvme_delete_cq(dev, qid);
537 static int nvme_set_queue_count(struct nvme_dev *dev, int count)
541 u32 q_count = (count - 1) | ((count - 1) << 16);
543 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES,
544 q_count, 0, &result);
551 return min(result & 0xffff, result >> 16) + 1;
554 static void nvme_create_io_queues(struct nvme_dev *dev)
558 for (i = dev->queue_count; i <= dev->max_qid; i++)
559 if (!nvme_alloc_queue(dev, i, dev->q_depth))
562 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
563 if (nvme_create_queue(dev->queues[i], i))
567 static int nvme_setup_io_queues(struct nvme_dev *dev)
573 result = nvme_set_queue_count(dev, nr_io_queues);
577 dev->max_qid = nr_io_queues;
579 /* Free previously allocated queues */
580 nvme_free_queues(dev, nr_io_queues + 1);
581 nvme_create_io_queues(dev);
586 static int nvme_get_info_from_identify(struct nvme_dev *dev)
588 struct nvme_id_ctrl *ctrl;
590 int shift = NVME_CAP_MPSMIN(dev->cap) + 12;
592 ctrl = memalign(dev->page_size, sizeof(struct nvme_id_ctrl));
596 ret = nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl);
602 dev->nn = le32_to_cpu(ctrl->nn);
603 dev->vwc = ctrl->vwc;
604 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
605 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
606 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
608 dev->max_transfer_shift = (ctrl->mdts + shift);
611 * Maximum Data Transfer Size (MDTS) field indicates the maximum
612 * data transfer size between the host and the controller. The
613 * host should not submit a command that exceeds this transfer
614 * size. The value is in units of the minimum memory page size
615 * and is reported as a power of two (2^n).
617 * The spec also says: a value of 0h indicates no restrictions
618 * on transfer size. But in nvme_blk_read/write() below we have
619 * the following algorithm for maximum number of logic blocks
622 * u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
624 * In order for lbas not to overflow, the maximum number is 15
625 * which means dev->max_transfer_shift = 15 + 9 (ns->lba_shift).
626 * Let's use 20 which provides 1MB size.
628 dev->max_transfer_shift = 20;
635 int nvme_get_namespace_id(struct udevice *udev, u32 *ns_id, u8 *eui64)
637 struct nvme_ns *ns = dev_get_priv(udev);
642 memcpy(eui64, ns->eui64, sizeof(ns->eui64));
647 int nvme_scan_namespace(void)
653 ret = uclass_get(UCLASS_NVME, &uc);
657 uclass_foreach_dev(dev, uc) {
658 ret = device_probe(dev);
666 static int nvme_blk_probe(struct udevice *udev)
668 struct nvme_dev *ndev = dev_get_priv(udev->parent);
669 struct blk_desc *desc = dev_get_uclass_platdata(udev);
670 struct nvme_ns *ns = dev_get_priv(udev);
672 struct pci_child_platdata *pplat;
673 struct nvme_id_ns *id;
675 id = memalign(ndev->page_size, sizeof(struct nvme_id_ns));
679 memset(ns, 0, sizeof(*ns));
681 /* extract the namespace id from the block device name */
682 ns->ns_id = trailing_strtol(udev->name) + 1;
683 if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id)) {
688 memcpy(&ns->eui64, &id->eui64, sizeof(id->eui64));
689 flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK;
691 ns->lba_shift = id->lbaf[flbas].ds;
692 ns->mode_select_num_blocks = le64_to_cpu(id->nsze);
693 ns->mode_select_block_len = 1 << ns->lba_shift;
694 list_add(&ns->list, &ndev->namespaces);
696 desc->lba = ns->mode_select_num_blocks;
697 desc->log2blksz = ns->lba_shift;
698 desc->blksz = 1 << ns->lba_shift;
700 pplat = dev_get_parent_platdata(udev->parent);
701 sprintf(desc->vendor, "0x%.4x", pplat->vendor);
702 memcpy(desc->product, ndev->serial, sizeof(ndev->serial));
703 memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev));
709 static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,
710 lbaint_t blkcnt, void *buffer, bool read)
712 struct nvme_ns *ns = dev_get_priv(udev);
713 struct nvme_dev *dev = ns->dev;
714 struct nvme_command c;
715 struct blk_desc *desc = dev_get_uclass_platdata(udev);
718 u64 total_len = blkcnt << desc->log2blksz;
719 u64 temp_len = total_len;
722 u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
723 u64 total_lbas = blkcnt;
725 flush_dcache_range((unsigned long)buffer,
726 (unsigned long)buffer + total_len);
728 c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write;
730 c.rw.nsid = cpu_to_le32(ns->ns_id);
739 if (total_lbas < lbas) {
740 lbas = (u16)total_lbas;
746 if (nvme_setup_prps(dev, &prp2,
747 lbas << ns->lba_shift, (ulong)buffer))
749 c.rw.slba = cpu_to_le64(slba);
751 c.rw.length = cpu_to_le16(lbas - 1);
752 c.rw.prp1 = cpu_to_le64((ulong)buffer);
753 c.rw.prp2 = cpu_to_le64(prp2);
754 status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
755 &c, NULL, IO_TIMEOUT);
758 temp_len -= (u32)lbas << ns->lba_shift;
759 buffer += lbas << ns->lba_shift;
763 invalidate_dcache_range((unsigned long)buffer,
764 (unsigned long)buffer + total_len);
766 return (total_len - temp_len) >> desc->log2blksz;
769 static ulong nvme_blk_read(struct udevice *udev, lbaint_t blknr,
770 lbaint_t blkcnt, void *buffer)
772 return nvme_blk_rw(udev, blknr, blkcnt, buffer, true);
775 static ulong nvme_blk_write(struct udevice *udev, lbaint_t blknr,
776 lbaint_t blkcnt, const void *buffer)
778 return nvme_blk_rw(udev, blknr, blkcnt, (void *)buffer, false);
781 static const struct blk_ops nvme_blk_ops = {
782 .read = nvme_blk_read,
783 .write = nvme_blk_write,
786 U_BOOT_DRIVER(nvme_blk) = {
789 .probe = nvme_blk_probe,
790 .ops = &nvme_blk_ops,
791 .priv_auto_alloc_size = sizeof(struct nvme_ns),
794 static int nvme_bind(struct udevice *udev)
799 sprintf(name, "nvme#%d", ndev_num++);
801 return device_set_name(udev, name);
804 static int nvme_probe(struct udevice *udev)
807 struct nvme_dev *ndev = dev_get_priv(udev);
809 ndev->instance = trailing_strtol(udev->name);
811 INIT_LIST_HEAD(&ndev->namespaces);
812 ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0,
814 if (readl(&ndev->bar->csts) == -1) {
816 printf("Error: %s: Out of memory!\n", udev->name);
820 ndev->queues = malloc(NVME_Q_NUM * sizeof(struct nvme_queue *));
823 printf("Error: %s: Out of memory!\n", udev->name);
826 memset(ndev->queues, 0, NVME_Q_NUM * sizeof(struct nvme_queue *));
828 ndev->cap = nvme_readq(&ndev->bar->cap);
829 ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH);
830 ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap);
831 ndev->dbs = ((void __iomem *)ndev->bar) + 4096;
833 ret = nvme_configure_admin_queue(ndev);
837 /* Allocate after the page size is known */
838 ndev->prp_pool = memalign(ndev->page_size, MAX_PRP_POOL);
839 if (!ndev->prp_pool) {
841 printf("Error: %s: Out of memory!\n", udev->name);
844 ndev->prp_entry_num = MAX_PRP_POOL >> 3;
846 ret = nvme_setup_io_queues(ndev);
850 nvme_get_info_from_identify(ndev);
855 free((void *)ndev->queues);
860 U_BOOT_DRIVER(nvme) = {
865 .priv_auto_alloc_size = sizeof(struct nvme_dev),
868 struct pci_device_id nvme_supported[] = {
869 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) },
873 U_BOOT_PCI_DEVICE(nvme, nvme_supported);