1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011 Michal Simek
5 * Michal SIMEK <monstr@monstr.eu>
7 * Based on Xilinx gmac driver:
8 * (C) Copyright 2011 Xilinx
24 #include <asm/system.h>
25 #include <asm/arch/hardware.h>
26 #include <asm/arch/sys_proto.h>
27 #include <linux/errno.h>
29 /* Bit/mask specification */
30 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
31 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
32 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
33 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
34 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
36 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
37 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
38 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
40 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
41 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
42 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
44 /* Wrap bit, last descriptor */
45 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
46 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
47 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
49 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
50 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
51 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
52 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
54 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
55 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
56 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
57 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
58 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
59 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
67 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
69 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
72 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
73 ZYNQ_GEM_NWCFG_FDEN | \
74 ZYNQ_GEM_NWCFG_FSREM | \
75 ZYNQ_GEM_NWCFG_MDCCLKDIV)
77 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
79 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
80 /* Use full configured addressable space (8 Kb) */
81 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
82 /* Use full configured addressable space (4 Kb) */
83 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
84 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
85 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
87 #if defined(CONFIG_PHYS_64BIT)
88 # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
90 # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
93 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
94 ZYNQ_GEM_DMACR_RXSIZE | \
95 ZYNQ_GEM_DMACR_TXSIZE | \
96 ZYNQ_GEM_DMACR_RXBUF | \
97 ZYNQ_GEM_DMA_BUS_WIDTH)
99 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
101 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
103 #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
105 /* Use MII register 1 (MII status register) to detect PHY */
106 #define PHY_DETECT_REG 1
108 /* Mask used to verify certain PHY features (or register contents)
109 * in the register above:
110 * 0x1000: 10Mbps full duplex support
111 * 0x0800: 10Mbps half duplex support
112 * 0x0008: Auto-negotiation support
114 #define PHY_DETECT_MASK 0x1808
116 /* TX BD status masks */
117 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
118 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
119 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
121 /* Clock frequencies for different speeds */
122 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
123 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
124 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
126 /* Device registers */
127 struct zynq_gem_regs {
128 u32 nwctrl; /* 0x0 - Network Control reg */
129 u32 nwcfg; /* 0x4 - Network Config reg */
130 u32 nwsr; /* 0x8 - Network Status reg */
132 u32 dmacr; /* 0x10 - DMA Control reg */
133 u32 txsr; /* 0x14 - TX Status reg */
134 u32 rxqbase; /* 0x18 - RX Q Base address reg */
135 u32 txqbase; /* 0x1c - TX Q Base address reg */
136 u32 rxsr; /* 0x20 - RX Status reg */
138 u32 idr; /* 0x2c - Interrupt Disable reg */
140 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
142 u32 hashl; /* 0x80 - Hash Low address reg */
143 u32 hashh; /* 0x84 - Hash High address reg */
146 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
147 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
150 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
154 u32 dcfg6; /* 0x294 Design config reg6 */
156 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
158 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
160 u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
162 u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
167 u32 addr; /* Next descriptor pointer */
169 #if defined(CONFIG_PHYS_64BIT)
176 /* Page table entries are set to 1MB, or multiples of 1MB
177 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
179 #define BD_SPACE 0x100000
180 /* BD separation space */
181 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
183 /* Setup the first free TX descriptor */
184 #define TX_FREE_DESC 2
186 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
187 struct zynq_gem_priv {
188 struct emac_bd *tx_bd;
189 struct emac_bd *rx_bd;
195 struct zynq_gem_regs *iobase;
196 phy_interface_t interface;
197 struct phy_device *phydev;
206 static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
210 struct zynq_gem_regs *regs = priv->iobase;
213 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
218 /* Construct mgtcr mask for the operation */
219 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
220 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
221 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
223 /* Write mgtcr and wait for completion */
224 writel(mgtcr, ®s->phymntnc);
226 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
231 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
232 *data = readl(®s->phymntnc);
237 static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
238 u32 regnum, u16 *val)
242 ret = phy_setup_op(priv, phy_addr, regnum,
243 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
246 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
247 phy_addr, regnum, *val);
252 static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
253 u32 regnum, u16 data)
255 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
258 return phy_setup_op(priv, phy_addr, regnum,
259 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
262 static int zynq_gem_setup_mac(struct udevice *dev)
264 u32 i, macaddrlow, macaddrhigh;
265 struct eth_pdata *pdata = dev_get_platdata(dev);
266 struct zynq_gem_priv *priv = dev_get_priv(dev);
267 struct zynq_gem_regs *regs = priv->iobase;
269 /* Set the MAC bits [31:0] in BOT */
270 macaddrlow = pdata->enetaddr[0];
271 macaddrlow |= pdata->enetaddr[1] << 8;
272 macaddrlow |= pdata->enetaddr[2] << 16;
273 macaddrlow |= pdata->enetaddr[3] << 24;
275 /* Set MAC bits [47:32] in TOP */
276 macaddrhigh = pdata->enetaddr[4];
277 macaddrhigh |= pdata->enetaddr[5] << 8;
279 for (i = 0; i < 4; i++) {
280 writel(0, ®s->laddr[i][LADDR_LOW]);
281 writel(0, ®s->laddr[i][LADDR_HIGH]);
282 /* Do not use MATCHx register */
283 writel(0, ®s->match[i]);
286 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
287 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
292 static int zynq_phy_init(struct udevice *dev)
295 struct zynq_gem_priv *priv = dev_get_priv(dev);
296 struct zynq_gem_regs *regs = priv->iobase;
297 const u32 supported = SUPPORTED_10baseT_Half |
298 SUPPORTED_10baseT_Full |
299 SUPPORTED_100baseT_Half |
300 SUPPORTED_100baseT_Full |
301 SUPPORTED_1000baseT_Half |
302 SUPPORTED_1000baseT_Full;
304 /* Enable only MDIO bus */
305 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
307 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
312 if (priv->max_speed) {
313 ret = phy_set_supported(priv->phydev, priv->max_speed);
318 priv->phydev->supported &= supported | ADVERTISED_Pause |
319 ADVERTISED_Asym_Pause;
321 priv->phydev->advertising = priv->phydev->supported;
322 priv->phydev->node = priv->phy_of_node;
324 return phy_config(priv->phydev);
327 static int zynq_gem_init(struct udevice *dev)
331 unsigned long clk_rate = 0;
332 struct zynq_gem_priv *priv = dev_get_priv(dev);
333 struct zynq_gem_regs *regs = priv->iobase;
334 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
335 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
337 if (readl(®s->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
338 priv->dma_64bit = true;
340 priv->dma_64bit = false;
342 #if defined(CONFIG_PHYS_64BIT)
343 if (!priv->dma_64bit) {
344 printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
350 debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
355 /* Disable all interrupts */
356 writel(0xFFFFFFFF, ®s->idr);
358 /* Disable the receiver & transmitter */
359 writel(0, ®s->nwctrl);
360 writel(0, ®s->txsr);
361 writel(0, ®s->rxsr);
362 writel(0, ®s->phymntnc);
364 /* Clear the Hash registers for the mac address
365 * pointed by AddressPtr
367 writel(0x0, ®s->hashl);
368 /* Write bits [63:32] in TOP */
369 writel(0x0, ®s->hashh);
371 /* Clear all counters */
372 for (i = 0; i < STAT_SIZE; i++)
373 readl(®s->stat[i]);
375 /* Setup RxBD space */
376 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
378 for (i = 0; i < RX_BUF; i++) {
379 priv->rx_bd[i].status = 0xF0000000;
380 priv->rx_bd[i].addr =
381 (lower_32_bits((ulong)(priv->rxbuffers)
382 + (i * PKTSIZE_ALIGN)));
383 #if defined(CONFIG_PHYS_64BIT)
384 priv->rx_bd[i].addr_hi =
385 (upper_32_bits((ulong)(priv->rxbuffers)
386 + (i * PKTSIZE_ALIGN)));
389 /* WRAP bit to last BD */
390 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
391 /* Write RxBDs to IP */
392 writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase);
393 #if defined(CONFIG_PHYS_64BIT)
394 writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase);
397 /* Setup for DMA Configuration register */
398 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
400 /* Setup for Network Control register, MDIO, Rx and Tx enable */
401 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
403 /* Disable the second priority queue */
404 dummy_tx_bd->addr = 0;
405 #if defined(CONFIG_PHYS_64BIT)
406 dummy_tx_bd->addr_hi = 0;
408 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
409 ZYNQ_GEM_TXBUF_LAST_MASK|
410 ZYNQ_GEM_TXBUF_USED_MASK;
412 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
413 ZYNQ_GEM_RXBUF_NEW_MASK;
414 #if defined(CONFIG_PHYS_64BIT)
415 dummy_rx_bd->addr_hi = 0;
417 dummy_rx_bd->status = 0;
419 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
420 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
425 ret = phy_startup(priv->phydev);
429 if (!priv->phydev->link) {
430 printf("%s: No link.\n", priv->phydev->dev->name);
434 nwconfig = ZYNQ_GEM_NWCFG_INIT;
437 * Set SGMII enable PCS selection only if internal PCS/PMA
438 * core is used and interface is SGMII.
440 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
442 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
443 ZYNQ_GEM_NWCFG_PCS_SEL;
445 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
450 switch (priv->phydev->speed) {
452 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
454 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
457 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
459 clk_rate = ZYNQ_GEM_FREQUENCY_100;
462 clk_rate = ZYNQ_GEM_FREQUENCY_10;
466 ret = clk_set_rate(&priv->clk, clk_rate);
467 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
468 dev_err(dev, "failed to set tx clock rate\n");
472 ret = clk_enable(&priv->clk);
473 if (ret && ret != -ENOSYS) {
474 dev_err(dev, "failed to enable tx clock\n");
478 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
479 ZYNQ_GEM_NWCTRL_TXEN_MASK);
484 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
488 struct zynq_gem_priv *priv = dev_get_priv(dev);
489 struct zynq_gem_regs *regs = priv->iobase;
490 struct emac_bd *current_bd = &priv->tx_bd[1];
493 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
495 priv->tx_bd->addr = lower_32_bits((ulong)ptr);
496 #if defined(CONFIG_PHYS_64BIT)
497 priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
499 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
500 ZYNQ_GEM_TXBUF_LAST_MASK;
501 /* Dummy descriptor to mark it as the last in descriptor chain */
502 current_bd->addr = 0x0;
503 #if defined(CONFIG_PHYS_64BIT)
504 current_bd->addr_hi = 0x0;
506 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
507 ZYNQ_GEM_TXBUF_LAST_MASK|
508 ZYNQ_GEM_TXBUF_USED_MASK;
511 writel(lower_32_bits((ulong)priv->tx_bd), ®s->txqbase);
512 #if defined(CONFIG_PHYS_64BIT)
513 writel(upper_32_bits((ulong)priv->tx_bd), ®s->upper_txqbase);
517 addr &= ~(ARCH_DMA_MINALIGN - 1);
518 size = roundup(len, ARCH_DMA_MINALIGN);
519 flush_dcache_range(addr, addr + size);
523 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
525 /* Read TX BD status */
526 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
527 printf("TX buffers exhausted in mid frame\n");
529 return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE,
533 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
534 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
538 struct zynq_gem_priv *priv = dev_get_priv(dev);
539 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
541 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
544 if (!(current_bd->status &
545 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
546 printf("GEM: SOF or EOF not set for last buffer received!\n");
550 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
552 printf("%s: Zero size packet?\n", __func__);
556 #if defined(CONFIG_PHYS_64BIT)
557 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
558 | ((dma_addr_t)current_bd->addr_hi << 32));
560 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
562 addr &= ~(ARCH_DMA_MINALIGN - 1);
564 *packetp = (uchar *)(uintptr_t)addr;
566 invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
572 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
574 struct zynq_gem_priv *priv = dev_get_priv(dev);
575 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
576 struct emac_bd *first_bd;
578 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
579 priv->rx_first_buf = priv->rxbd_current;
581 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
582 current_bd->status = 0xF0000000; /* FIXME */
585 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
586 first_bd = &priv->rx_bd[priv->rx_first_buf];
587 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
588 first_bd->status = 0xF0000000;
591 if ((++priv->rxbd_current) >= RX_BUF)
592 priv->rxbd_current = 0;
597 static void zynq_gem_halt(struct udevice *dev)
599 struct zynq_gem_priv *priv = dev_get_priv(dev);
600 struct zynq_gem_regs *regs = priv->iobase;
602 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
603 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
606 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
611 static int zynq_gem_read_rom_mac(struct udevice *dev)
613 struct eth_pdata *pdata = dev_get_platdata(dev);
618 return zynq_board_read_rom_ethaddr(pdata->enetaddr);
621 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
624 struct zynq_gem_priv *priv = bus->priv;
628 ret = phyread(priv, addr, reg, &val);
629 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
633 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
636 struct zynq_gem_priv *priv = bus->priv;
638 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
639 return phywrite(priv, addr, reg, value);
642 static int zynq_gem_probe(struct udevice *dev)
645 struct zynq_gem_priv *priv = dev_get_priv(dev);
648 /* Align rxbuffers to ARCH_DMA_MINALIGN */
649 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
650 if (!priv->rxbuffers)
653 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
654 u32 addr = (ulong)priv->rxbuffers;
655 flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
658 /* Align bd_space to MMU_SECTION_SHIFT */
659 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
663 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
664 BD_SPACE, DCACHE_OFF);
666 /* Initialize the bd spaces for tx and rx bd's */
667 priv->tx_bd = (struct emac_bd *)bd_space;
668 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
670 ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
672 dev_err(dev, "failed to get clock\n");
676 priv->bus = mdio_alloc();
677 priv->bus->read = zynq_gem_miiphy_read;
678 priv->bus->write = zynq_gem_miiphy_write;
679 priv->bus->priv = priv;
681 ret = mdio_register_seq(priv->bus, dev->seq);
685 return zynq_phy_init(dev);
688 static int zynq_gem_remove(struct udevice *dev)
690 struct zynq_gem_priv *priv = dev_get_priv(dev);
693 mdio_unregister(priv->bus);
694 mdio_free(priv->bus);
699 static const struct eth_ops zynq_gem_ops = {
700 .start = zynq_gem_init,
701 .send = zynq_gem_send,
702 .recv = zynq_gem_recv,
703 .free_pkt = zynq_gem_free_pkt,
704 .stop = zynq_gem_halt,
705 .write_hwaddr = zynq_gem_setup_mac,
706 .read_rom_hwaddr = zynq_gem_read_rom_mac,
709 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
711 struct eth_pdata *pdata = dev_get_platdata(dev);
712 struct zynq_gem_priv *priv = dev_get_priv(dev);
713 struct ofnode_phandle_args phandle_args;
714 const char *phy_mode;
716 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
717 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
718 /* Hardcode for now */
721 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
723 debug("phy-handle does exist %s\n", dev->name);
724 priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
726 priv->phy_of_node = phandle_args.node;
727 priv->max_speed = ofnode_read_u32_default(phandle_args.node,
732 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
734 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
735 if (pdata->phy_interface == -1) {
736 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
739 priv->interface = pdata->phy_interface;
741 priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
743 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
744 priv->phyaddr, phy_string_for_interface(priv->interface));
749 static const struct udevice_id zynq_gem_ids[] = {
750 { .compatible = "cdns,versal-gem" },
751 { .compatible = "cdns,zynqmp-gem" },
752 { .compatible = "cdns,zynq-gem" },
753 { .compatible = "cdns,gem" },
757 U_BOOT_DRIVER(zynq_gem) = {
760 .of_match = zynq_gem_ids,
761 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
762 .probe = zynq_gem_probe,
763 .remove = zynq_gem_remove,
764 .ops = &zynq_gem_ops,
765 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
766 .platdata_auto_alloc_size = sizeof(struct eth_pdata),