1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011 Michal Simek
5 * Michal SIMEK <monstr@monstr.eu>
7 * Based on Xilinx gmac driver:
8 * (C) Copyright 2011 Xilinx
25 #include <asm/system.h>
26 #include <asm/arch/hardware.h>
27 #include <asm/arch/sys_proto.h>
28 #include <dm/device_compat.h>
29 #include <linux/err.h>
30 #include <linux/errno.h>
32 /* Bit/mask specification */
33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
47 /* Wrap bit, last descriptor */
48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
57 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
59 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
60 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
61 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
62 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
66 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
70 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
72 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
75 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
76 ZYNQ_GEM_NWCFG_FDEN | \
77 ZYNQ_GEM_NWCFG_FSREM | \
78 ZYNQ_GEM_NWCFG_MDCCLKDIV)
80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
83 /* Use full configured addressable space (8 Kb) */
84 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
85 /* Use full configured addressable space (4 Kb) */
86 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
87 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
88 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
90 #if defined(CONFIG_PHYS_64BIT)
91 # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
93 # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
96 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
97 ZYNQ_GEM_DMACR_RXSIZE | \
98 ZYNQ_GEM_DMACR_TXSIZE | \
99 ZYNQ_GEM_DMACR_RXBUF | \
100 ZYNQ_GEM_DMA_BUS_WIDTH)
102 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
104 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
106 #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
108 /* Use MII register 1 (MII status register) to detect PHY */
109 #define PHY_DETECT_REG 1
111 /* Mask used to verify certain PHY features (or register contents)
112 * in the register above:
113 * 0x1000: 10Mbps full duplex support
114 * 0x0800: 10Mbps half duplex support
115 * 0x0008: Auto-negotiation support
117 #define PHY_DETECT_MASK 0x1808
119 /* TX BD status masks */
120 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
121 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
122 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
124 /* Clock frequencies for different speeds */
125 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
126 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
127 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
129 /* Device registers */
130 struct zynq_gem_regs {
131 u32 nwctrl; /* 0x0 - Network Control reg */
132 u32 nwcfg; /* 0x4 - Network Config reg */
133 u32 nwsr; /* 0x8 - Network Status reg */
135 u32 dmacr; /* 0x10 - DMA Control reg */
136 u32 txsr; /* 0x14 - TX Status reg */
137 u32 rxqbase; /* 0x18 - RX Q Base address reg */
138 u32 txqbase; /* 0x1c - TX Q Base address reg */
139 u32 rxsr; /* 0x20 - RX Status reg */
141 u32 idr; /* 0x2c - Interrupt Disable reg */
143 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
145 u32 hashl; /* 0x80 - Hash Low address reg */
146 u32 hashh; /* 0x84 - Hash High address reg */
149 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
150 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
153 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
157 u32 dcfg6; /* 0x294 Design config reg6 */
159 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
161 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
163 u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
165 u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
170 u32 addr; /* Next descriptor pointer */
172 #if defined(CONFIG_PHYS_64BIT)
178 /* Reduce amount of BUFs if you have limited amount of memory */
180 /* Page table entries are set to 1MB, or multiples of 1MB
181 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
183 #define BD_SPACE 0x100000
184 /* BD separation space */
185 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
187 /* Setup the first free TX descriptor */
188 #define TX_FREE_DESC 2
190 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
191 struct zynq_gem_priv {
192 struct emac_bd *tx_bd;
193 struct emac_bd *rx_bd;
199 struct zynq_gem_regs *iobase;
200 struct zynq_gem_regs *mdiobase;
201 phy_interface_t interface;
202 struct phy_device *phydev;
211 static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
215 struct zynq_gem_regs *regs = priv->mdiobase;
218 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
223 /* Construct mgtcr mask for the operation */
224 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
225 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
226 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
228 /* Write mgtcr and wait for completion */
229 writel(mgtcr, ®s->phymntnc);
231 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
236 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
237 *data = readl(®s->phymntnc);
242 static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
243 u32 regnum, u16 *val)
247 ret = phy_setup_op(priv, phy_addr, regnum,
248 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
251 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
252 phy_addr, regnum, *val);
257 static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
258 u32 regnum, u16 data)
260 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
263 return phy_setup_op(priv, phy_addr, regnum,
264 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
267 static int zynq_gem_setup_mac(struct udevice *dev)
269 u32 i, macaddrlow, macaddrhigh;
270 struct eth_pdata *pdata = dev_get_platdata(dev);
271 struct zynq_gem_priv *priv = dev_get_priv(dev);
272 struct zynq_gem_regs *regs = priv->iobase;
274 /* Set the MAC bits [31:0] in BOT */
275 macaddrlow = pdata->enetaddr[0];
276 macaddrlow |= pdata->enetaddr[1] << 8;
277 macaddrlow |= pdata->enetaddr[2] << 16;
278 macaddrlow |= pdata->enetaddr[3] << 24;
280 /* Set MAC bits [47:32] in TOP */
281 macaddrhigh = pdata->enetaddr[4];
282 macaddrhigh |= pdata->enetaddr[5] << 8;
284 for (i = 0; i < 4; i++) {
285 writel(0, ®s->laddr[i][LADDR_LOW]);
286 writel(0, ®s->laddr[i][LADDR_HIGH]);
287 /* Do not use MATCHx register */
288 writel(0, ®s->match[i]);
291 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
292 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
297 static int zynq_phy_init(struct udevice *dev)
300 struct zynq_gem_priv *priv = dev_get_priv(dev);
301 struct zynq_gem_regs *regs_mdio = priv->mdiobase;
302 const u32 supported = SUPPORTED_10baseT_Half |
303 SUPPORTED_10baseT_Full |
304 SUPPORTED_100baseT_Half |
305 SUPPORTED_100baseT_Full |
306 SUPPORTED_1000baseT_Half |
307 SUPPORTED_1000baseT_Full;
309 /* Enable only MDIO bus */
310 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl);
312 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
317 if (priv->max_speed) {
318 ret = phy_set_supported(priv->phydev, priv->max_speed);
323 priv->phydev->supported &= supported | ADVERTISED_Pause |
324 ADVERTISED_Asym_Pause;
326 priv->phydev->advertising = priv->phydev->supported;
327 priv->phydev->node = priv->phy_of_node;
329 return phy_config(priv->phydev);
332 static int zynq_gem_init(struct udevice *dev)
336 unsigned long clk_rate = 0;
337 struct zynq_gem_priv *priv = dev_get_priv(dev);
338 struct zynq_gem_regs *regs = priv->iobase;
339 struct zynq_gem_regs *regs_mdio = priv->mdiobase;
340 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
341 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
343 if (readl(®s->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
344 priv->dma_64bit = true;
346 priv->dma_64bit = false;
348 #if defined(CONFIG_PHYS_64BIT)
349 if (!priv->dma_64bit) {
350 printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
356 debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
361 /* Disable all interrupts */
362 writel(0xFFFFFFFF, ®s->idr);
364 /* Disable the receiver & transmitter */
365 writel(0, ®s->nwctrl);
366 writel(0, ®s->txsr);
367 writel(0, ®s->rxsr);
368 writel(0, ®s->phymntnc);
370 /* Clear the Hash registers for the mac address
371 * pointed by AddressPtr
373 writel(0x0, ®s->hashl);
374 /* Write bits [63:32] in TOP */
375 writel(0x0, ®s->hashh);
377 /* Clear all counters */
378 for (i = 0; i < STAT_SIZE; i++)
379 readl(®s->stat[i]);
381 /* Setup RxBD space */
382 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
384 for (i = 0; i < RX_BUF; i++) {
385 priv->rx_bd[i].status = 0xF0000000;
386 priv->rx_bd[i].addr =
387 (lower_32_bits((ulong)(priv->rxbuffers)
388 + (i * PKTSIZE_ALIGN)));
389 #if defined(CONFIG_PHYS_64BIT)
390 priv->rx_bd[i].addr_hi =
391 (upper_32_bits((ulong)(priv->rxbuffers)
392 + (i * PKTSIZE_ALIGN)));
395 /* WRAP bit to last BD */
396 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
397 /* Write RxBDs to IP */
398 writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase);
399 #if defined(CONFIG_PHYS_64BIT)
400 writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase);
403 /* Setup for DMA Configuration register */
404 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
406 /* Setup for Network Control register, MDIO, Rx and Tx enable */
407 setbits_le32(®s_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
409 /* Disable the second priority queue */
410 dummy_tx_bd->addr = 0;
411 #if defined(CONFIG_PHYS_64BIT)
412 dummy_tx_bd->addr_hi = 0;
414 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
415 ZYNQ_GEM_TXBUF_LAST_MASK|
416 ZYNQ_GEM_TXBUF_USED_MASK;
418 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
419 ZYNQ_GEM_RXBUF_NEW_MASK;
420 #if defined(CONFIG_PHYS_64BIT)
421 dummy_rx_bd->addr_hi = 0;
423 dummy_rx_bd->status = 0;
425 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
426 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
431 ret = phy_startup(priv->phydev);
435 if (!priv->phydev->link) {
436 printf("%s: No link.\n", priv->phydev->dev->name);
440 nwconfig = ZYNQ_GEM_NWCFG_INIT;
443 * Set SGMII enable PCS selection only if internal PCS/PMA
444 * core is used and interface is SGMII.
446 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
448 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
449 ZYNQ_GEM_NWCFG_PCS_SEL;
451 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
456 switch (priv->phydev->speed) {
458 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
460 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
463 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
465 clk_rate = ZYNQ_GEM_FREQUENCY_100;
468 clk_rate = ZYNQ_GEM_FREQUENCY_10;
472 ret = clk_set_rate(&priv->clk, clk_rate);
473 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
474 dev_err(dev, "failed to set tx clock rate\n");
478 ret = clk_enable(&priv->clk);
479 if (ret && ret != -ENOSYS) {
480 dev_err(dev, "failed to enable tx clock\n");
484 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
485 ZYNQ_GEM_NWCTRL_TXEN_MASK);
490 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
494 struct zynq_gem_priv *priv = dev_get_priv(dev);
495 struct zynq_gem_regs *regs = priv->iobase;
496 struct emac_bd *current_bd = &priv->tx_bd[1];
499 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
501 priv->tx_bd->addr = lower_32_bits((ulong)ptr);
502 #if defined(CONFIG_PHYS_64BIT)
503 priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
505 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
506 ZYNQ_GEM_TXBUF_LAST_MASK;
507 /* Dummy descriptor to mark it as the last in descriptor chain */
508 current_bd->addr = 0x0;
509 #if defined(CONFIG_PHYS_64BIT)
510 current_bd->addr_hi = 0x0;
512 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
513 ZYNQ_GEM_TXBUF_LAST_MASK|
514 ZYNQ_GEM_TXBUF_USED_MASK;
517 writel(lower_32_bits((ulong)priv->tx_bd), ®s->txqbase);
518 #if defined(CONFIG_PHYS_64BIT)
519 writel(upper_32_bits((ulong)priv->tx_bd), ®s->upper_txqbase);
523 addr &= ~(ARCH_DMA_MINALIGN - 1);
524 size = roundup(len, ARCH_DMA_MINALIGN);
525 flush_dcache_range(addr, addr + size);
529 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
531 /* Read TX BD status */
532 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
533 printf("TX buffers exhausted in mid frame\n");
535 return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE,
539 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
540 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
544 struct zynq_gem_priv *priv = dev_get_priv(dev);
545 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
547 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
550 if (!(current_bd->status &
551 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
552 printf("GEM: SOF or EOF not set for last buffer received!\n");
556 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
558 printf("%s: Zero size packet?\n", __func__);
562 #if defined(CONFIG_PHYS_64BIT)
563 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
564 | ((dma_addr_t)current_bd->addr_hi << 32));
566 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
568 addr &= ~(ARCH_DMA_MINALIGN - 1);
570 *packetp = (uchar *)(uintptr_t)addr;
572 invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
578 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
580 struct zynq_gem_priv *priv = dev_get_priv(dev);
581 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
582 struct emac_bd *first_bd;
585 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
586 priv->rx_first_buf = priv->rxbd_current;
588 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
589 current_bd->status = 0xF0000000; /* FIXME */
592 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
593 first_bd = &priv->rx_bd[priv->rx_first_buf];
594 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
595 first_bd->status = 0xF0000000;
598 /* Flush the cache for the packet as well */
599 #if defined(CONFIG_PHYS_64BIT)
600 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
601 | ((dma_addr_t)current_bd->addr_hi << 32));
603 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
605 flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN,
609 if ((++priv->rxbd_current) >= RX_BUF)
610 priv->rxbd_current = 0;
615 static void zynq_gem_halt(struct udevice *dev)
617 struct zynq_gem_priv *priv = dev_get_priv(dev);
618 struct zynq_gem_regs *regs = priv->iobase;
620 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
621 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
624 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
629 static int zynq_gem_read_rom_mac(struct udevice *dev)
631 struct eth_pdata *pdata = dev_get_platdata(dev);
636 return zynq_board_read_rom_ethaddr(pdata->enetaddr);
639 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
642 struct zynq_gem_priv *priv = bus->priv;
646 ret = phyread(priv, addr, reg, &val);
647 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
651 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
654 struct zynq_gem_priv *priv = bus->priv;
656 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
657 return phywrite(priv, addr, reg, value);
660 static int zynq_gem_probe(struct udevice *dev)
663 struct zynq_gem_priv *priv = dev_get_priv(dev);
666 /* Align rxbuffers to ARCH_DMA_MINALIGN */
667 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
668 if (!priv->rxbuffers)
671 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
672 ulong addr = (ulong)priv->rxbuffers;
673 flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
676 /* Align bd_space to MMU_SECTION_SHIFT */
677 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
683 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
684 BD_SPACE, DCACHE_OFF);
686 /* Initialize the bd spaces for tx and rx bd's */
687 priv->tx_bd = (struct emac_bd *)bd_space;
688 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
690 ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
692 dev_err(dev, "failed to get clock\n");
696 priv->bus = mdio_alloc();
697 priv->bus->read = zynq_gem_miiphy_read;
698 priv->bus->write = zynq_gem_miiphy_write;
699 priv->bus->priv = priv;
701 ret = mdio_register_seq(priv->bus, dev->seq);
705 ret = zynq_phy_init(dev);
712 free(priv->rxbuffers);
718 static int zynq_gem_remove(struct udevice *dev)
720 struct zynq_gem_priv *priv = dev_get_priv(dev);
723 mdio_unregister(priv->bus);
724 mdio_free(priv->bus);
729 static const struct eth_ops zynq_gem_ops = {
730 .start = zynq_gem_init,
731 .send = zynq_gem_send,
732 .recv = zynq_gem_recv,
733 .free_pkt = zynq_gem_free_pkt,
734 .stop = zynq_gem_halt,
735 .write_hwaddr = zynq_gem_setup_mac,
736 .read_rom_hwaddr = zynq_gem_read_rom_mac,
739 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
741 struct eth_pdata *pdata = dev_get_platdata(dev);
742 struct zynq_gem_priv *priv = dev_get_priv(dev);
743 struct ofnode_phandle_args phandle_args;
744 const char *phy_mode;
746 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
747 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
748 priv->mdiobase = priv->iobase;
749 /* Hardcode for now */
752 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
754 debug("phy-handle does exist %s\n", dev->name);
755 priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
757 priv->phy_of_node = phandle_args.node;
758 priv->max_speed = ofnode_read_u32_default(phandle_args.node,
763 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
765 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
766 if (pdata->phy_interface == -1) {
767 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
770 priv->interface = pdata->phy_interface;
772 priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
774 printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n",
775 (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr,
776 phy_string_for_interface(priv->interface));
781 static const struct udevice_id zynq_gem_ids[] = {
782 { .compatible = "cdns,versal-gem" },
783 { .compatible = "cdns,zynqmp-gem" },
784 { .compatible = "cdns,zynq-gem" },
785 { .compatible = "cdns,gem" },
789 U_BOOT_DRIVER(zynq_gem) = {
792 .of_match = zynq_gem_ids,
793 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
794 .probe = zynq_gem_probe,
795 .remove = zynq_gem_remove,
796 .ops = &zynq_gem_ops,
797 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
798 .platdata_auto_alloc_size = sizeof(struct eth_pdata),