2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/system.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm-generic/errno.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 /* Bit/mask specification */
31 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
32 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
33 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
34 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
35 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
37 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
38 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
39 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
41 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
42 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
43 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
45 /* Wrap bit, last descriptor */
46 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
47 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
48 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
50 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
51 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
52 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
53 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
55 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
56 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
57 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
58 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
59 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
62 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
64 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
67 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
68 ZYNQ_GEM_NWCFG_FDEN | \
69 ZYNQ_GEM_NWCFG_FSREM | \
70 ZYNQ_GEM_NWCFG_MDCCLKDIV)
72 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
74 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
75 /* Use full configured addressable space (8 Kb) */
76 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
77 /* Use full configured addressable space (4 Kb) */
78 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
79 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
80 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
82 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
83 ZYNQ_GEM_DMACR_RXSIZE | \
84 ZYNQ_GEM_DMACR_TXSIZE | \
87 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
89 /* Use MII register 1 (MII status register) to detect PHY */
90 #define PHY_DETECT_REG 1
92 /* Mask used to verify certain PHY features (or register contents)
93 * in the register above:
94 * 0x1000: 10Mbps full duplex support
95 * 0x0800: 10Mbps half duplex support
96 * 0x0008: Auto-negotiation support
98 #define PHY_DETECT_MASK 0x1808
100 /* TX BD status masks */
101 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
102 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
103 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
105 /* Clock frequencies for different speeds */
106 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
107 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
108 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
110 /* Device registers */
111 struct zynq_gem_regs {
112 u32 nwctrl; /* 0x0 - Network Control reg */
113 u32 nwcfg; /* 0x4 - Network Config reg */
114 u32 nwsr; /* 0x8 - Network Status reg */
116 u32 dmacr; /* 0x10 - DMA Control reg */
117 u32 txsr; /* 0x14 - TX Status reg */
118 u32 rxqbase; /* 0x18 - RX Q Base address reg */
119 u32 txqbase; /* 0x1c - TX Q Base address reg */
120 u32 rxsr; /* 0x20 - RX Status reg */
122 u32 idr; /* 0x2c - Interrupt Disable reg */
124 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
126 u32 hashl; /* 0x80 - Hash Low address reg */
127 u32 hashh; /* 0x84 - Hash High address reg */
130 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
131 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
134 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
136 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
138 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
143 u32 addr; /* Next descriptor pointer */
148 /* Page table entries are set to 1MB, or multiples of 1MB
149 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
151 #define BD_SPACE 0x100000
152 /* BD separation space */
153 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
155 /* Setup the first free TX descriptor */
156 #define TX_FREE_DESC 2
158 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
159 struct zynq_gem_priv {
160 struct emac_bd *tx_bd;
161 struct emac_bd *rx_bd;
168 struct zynq_gem_regs *iobase;
169 phy_interface_t interface;
170 struct phy_device *phydev;
174 static inline int mdio_wait(struct zynq_gem_regs *regs)
178 /* Wait till MDIO interface is ready to accept a new transaction. */
180 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
186 printf("%s: Timeout\n", __func__);
193 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
197 struct zynq_gem_regs *regs = priv->iobase;
202 /* Construct mgtcr mask for the operation */
203 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
204 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
205 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
207 /* Write mgtcr and wait for completion */
208 writel(mgtcr, ®s->phymntnc);
213 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
214 *data = readl(®s->phymntnc);
219 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
220 u32 regnum, u16 *val)
224 ret = phy_setup_op(priv, phy_addr, regnum,
225 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
228 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
229 phy_addr, regnum, *val);
234 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
235 u32 regnum, u16 data)
237 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
240 return phy_setup_op(priv, phy_addr, regnum,
241 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
244 static int phy_detection(struct udevice *dev)
248 struct zynq_gem_priv *priv = dev->priv;
250 if (priv->phyaddr != -1) {
251 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
252 if ((phyreg != 0xFFFF) &&
253 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
254 /* Found a valid PHY address */
255 debug("Default phy address %d is valid\n",
259 debug("PHY address is not setup correctly %d\n",
265 debug("detecting phy address\n");
266 if (priv->phyaddr == -1) {
267 /* detect the PHY address */
268 for (i = 31; i >= 0; i--) {
269 phyread(priv, i, PHY_DETECT_REG, &phyreg);
270 if ((phyreg != 0xFFFF) &&
271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
272 /* Found a valid PHY address */
274 debug("Found valid phy address, %d\n", i);
279 printf("PHY is not detected\n");
283 static int zynq_gem_setup_mac(struct udevice *dev)
285 u32 i, macaddrlow, macaddrhigh;
286 struct eth_pdata *pdata = dev_get_platdata(dev);
287 struct zynq_gem_priv *priv = dev_get_priv(dev);
288 struct zynq_gem_regs *regs = priv->iobase;
290 /* Set the MAC bits [31:0] in BOT */
291 macaddrlow = pdata->enetaddr[0];
292 macaddrlow |= pdata->enetaddr[1] << 8;
293 macaddrlow |= pdata->enetaddr[2] << 16;
294 macaddrlow |= pdata->enetaddr[3] << 24;
296 /* Set MAC bits [47:32] in TOP */
297 macaddrhigh = pdata->enetaddr[4];
298 macaddrhigh |= pdata->enetaddr[5] << 8;
300 for (i = 0; i < 4; i++) {
301 writel(0, ®s->laddr[i][LADDR_LOW]);
302 writel(0, ®s->laddr[i][LADDR_HIGH]);
303 /* Do not use MATCHx register */
304 writel(0, ®s->match[i]);
307 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
308 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
313 static int zynq_phy_init(struct udevice *dev)
316 struct zynq_gem_priv *priv = dev_get_priv(dev);
317 struct zynq_gem_regs *regs = priv->iobase;
318 const u32 supported = SUPPORTED_10baseT_Half |
319 SUPPORTED_10baseT_Full |
320 SUPPORTED_100baseT_Half |
321 SUPPORTED_100baseT_Full |
322 SUPPORTED_1000baseT_Half |
323 SUPPORTED_1000baseT_Full;
325 /* Enable only MDIO bus */
326 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
328 ret = phy_detection(dev);
330 printf("GEM PHY init failed\n");
334 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
339 priv->phydev->supported = supported | ADVERTISED_Pause |
340 ADVERTISED_Asym_Pause;
341 priv->phydev->advertising = priv->phydev->supported;
342 phy_config(priv->phydev);
347 static int zynq_gem_init(struct udevice *dev)
350 unsigned long clk_rate = 0;
351 struct zynq_gem_priv *priv = dev_get_priv(dev);
352 struct zynq_gem_regs *regs = priv->iobase;
353 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
354 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
357 /* Disable all interrupts */
358 writel(0xFFFFFFFF, ®s->idr);
360 /* Disable the receiver & transmitter */
361 writel(0, ®s->nwctrl);
362 writel(0, ®s->txsr);
363 writel(0, ®s->rxsr);
364 writel(0, ®s->phymntnc);
366 /* Clear the Hash registers for the mac address
367 * pointed by AddressPtr
369 writel(0x0, ®s->hashl);
370 /* Write bits [63:32] in TOP */
371 writel(0x0, ®s->hashh);
373 /* Clear all counters */
374 for (i = 0; i < STAT_SIZE; i++)
375 readl(®s->stat[i]);
377 /* Setup RxBD space */
378 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
380 for (i = 0; i < RX_BUF; i++) {
381 priv->rx_bd[i].status = 0xF0000000;
382 priv->rx_bd[i].addr =
383 ((ulong)(priv->rxbuffers) +
384 (i * PKTSIZE_ALIGN));
386 /* WRAP bit to last BD */
387 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
388 /* Write RxBDs to IP */
389 writel((ulong)priv->rx_bd, ®s->rxqbase);
391 /* Setup for DMA Configuration register */
392 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
394 /* Setup for Network Control register, MDIO, Rx and Tx enable */
395 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
397 /* Disable the second priority queue */
398 dummy_tx_bd->addr = 0;
399 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
400 ZYNQ_GEM_TXBUF_LAST_MASK|
401 ZYNQ_GEM_TXBUF_USED_MASK;
403 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
404 ZYNQ_GEM_RXBUF_NEW_MASK;
405 dummy_rx_bd->status = 0;
406 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
407 sizeof(dummy_tx_bd));
408 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
409 sizeof(dummy_rx_bd));
411 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
412 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
417 phy_startup(priv->phydev);
419 if (!priv->phydev->link) {
420 printf("%s: No link.\n", priv->phydev->dev->name);
424 switch (priv->phydev->speed) {
426 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
428 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
431 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
433 clk_rate = ZYNQ_GEM_FREQUENCY_100;
436 clk_rate = ZYNQ_GEM_FREQUENCY_10;
440 /* Change the rclk and clk only not using EMIO interface */
442 zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
443 ZYNQ_GEM_BASEADDR0, clk_rate);
445 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
446 ZYNQ_GEM_NWCTRL_TXEN_MASK);
451 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
452 bool set, unsigned int timeout)
455 unsigned long start = get_timer(0);
463 if ((val & mask) == mask)
466 if (get_timer(start) > timeout)
477 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
478 func, reg, mask, set);
483 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
486 struct zynq_gem_priv *priv = dev_get_priv(dev);
487 struct zynq_gem_regs *regs = priv->iobase;
488 struct emac_bd *current_bd = &priv->tx_bd[1];
491 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
493 priv->tx_bd->addr = (ulong)ptr;
494 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
495 ZYNQ_GEM_TXBUF_LAST_MASK;
496 /* Dummy descriptor to mark it as the last in descriptor chain */
497 current_bd->addr = 0x0;
498 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
499 ZYNQ_GEM_TXBUF_LAST_MASK|
500 ZYNQ_GEM_TXBUF_USED_MASK;
503 writel((ulong)priv->tx_bd, ®s->txqbase);
506 addr &= ~(ARCH_DMA_MINALIGN - 1);
507 size = roundup(len, ARCH_DMA_MINALIGN);
508 flush_dcache_range(addr, addr + size);
510 addr = (ulong)priv->rxbuffers;
511 addr &= ~(ARCH_DMA_MINALIGN - 1);
512 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
513 flush_dcache_range(addr, addr + size);
517 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
519 /* Read TX BD status */
520 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
521 printf("TX buffers exhausted in mid frame\n");
523 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
527 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
528 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
532 struct zynq_gem_priv *priv = dev_get_priv(dev);
533 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
535 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
538 if (!(current_bd->status &
539 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
540 printf("GEM: SOF or EOF not set for last buffer received!\n");
544 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
546 printf("%s: Zero size packet?\n", __func__);
550 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
551 addr &= ~(ARCH_DMA_MINALIGN - 1);
552 *packetp = (uchar *)(uintptr_t)addr;
557 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
559 struct zynq_gem_priv *priv = dev_get_priv(dev);
560 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
561 struct emac_bd *first_bd;
563 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
564 priv->rx_first_buf = priv->rxbd_current;
566 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
567 current_bd->status = 0xF0000000; /* FIXME */
570 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
571 first_bd = &priv->rx_bd[priv->rx_first_buf];
572 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
573 first_bd->status = 0xF0000000;
576 if ((++priv->rxbd_current) >= RX_BUF)
577 priv->rxbd_current = 0;
582 static void zynq_gem_halt(struct udevice *dev)
584 struct zynq_gem_priv *priv = dev_get_priv(dev);
585 struct zynq_gem_regs *regs = priv->iobase;
587 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
588 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
591 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
594 struct zynq_gem_priv *priv = bus->priv;
598 ret = phyread(priv, addr, reg, &val);
599 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
603 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
606 struct zynq_gem_priv *priv = bus->priv;
608 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
609 return phywrite(priv, addr, reg, value);
612 static int zynq_gem_probe(struct udevice *dev)
615 struct zynq_gem_priv *priv = dev_get_priv(dev);
618 /* Align rxbuffers to ARCH_DMA_MINALIGN */
619 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
620 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
622 /* Align bd_space to MMU_SECTION_SHIFT */
623 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
624 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
625 BD_SPACE, DCACHE_OFF);
627 /* Initialize the bd spaces for tx and rx bd's */
628 priv->tx_bd = (struct emac_bd *)bd_space;
629 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
631 priv->bus = mdio_alloc();
632 priv->bus->read = zynq_gem_miiphy_read;
633 priv->bus->write = zynq_gem_miiphy_write;
634 priv->bus->priv = priv;
635 strcpy(priv->bus->name, "gem");
637 ret = mdio_register(priv->bus);
646 static int zynq_gem_remove(struct udevice *dev)
648 struct zynq_gem_priv *priv = dev_get_priv(dev);
651 mdio_unregister(priv->bus);
652 mdio_free(priv->bus);
657 static const struct eth_ops zynq_gem_ops = {
658 .start = zynq_gem_init,
659 .send = zynq_gem_send,
660 .recv = zynq_gem_recv,
661 .free_pkt = zynq_gem_free_pkt,
662 .stop = zynq_gem_halt,
663 .write_hwaddr = zynq_gem_setup_mac,
666 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
668 struct eth_pdata *pdata = dev_get_platdata(dev);
669 struct zynq_gem_priv *priv = dev_get_priv(dev);
671 const char *phy_mode;
673 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
674 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
675 /* Hardcode for now */
679 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
682 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
684 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
686 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
687 if (pdata->phy_interface == -1) {
688 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
691 priv->interface = pdata->phy_interface;
693 printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
694 priv->phyaddr, phy_string_for_interface(priv->interface));
699 static const struct udevice_id zynq_gem_ids[] = {
700 { .compatible = "cdns,zynqmp-gem" },
701 { .compatible = "cdns,zynq-gem" },
702 { .compatible = "cdns,gem" },
706 U_BOOT_DRIVER(zynq_gem) = {
709 .of_match = zynq_gem_ids,
710 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
711 .probe = zynq_gem_probe,
712 .remove = zynq_gem_remove,
713 .ops = &zynq_gem_ops,
714 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
715 .platdata_auto_alloc_size = sizeof(struct eth_pdata),